| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.24 2002/11/22 01:57:06 mohor
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// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
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// synchronized.
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//
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// Revision 1.23 2002/11/19 18:13:49 mohor
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// Revision 1.23 2002/11/19 18:13:49 mohor
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// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
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// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
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//
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//
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// Revision 1.22 2002/11/14 18:37:20 mohor
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// Revision 1.22 2002/11/14 18:37:20 mohor
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// r_Rst signal does not reset any module any more and is removed from the design.
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// r_Rst signal does not reset any module any more and is removed from the design.
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| Line 291... |
Line 295... |
wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write;
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wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write;
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wire HASH0_Wr = (Address == `ETH_HASH0_ADR ) & Write;
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wire HASH0_Wr = (Address == `ETH_HASH0_ADR ) & Write;
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wire HASH1_Wr = (Address == `ETH_HASH1_ADR ) & Write;
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wire HASH1_Wr = (Address == `ETH_HASH1_ADR ) & Write;
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wire TXCTRL_Wr = (Address == `ETH_TX_CTRL_ADR ) & Write;
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wire TXCTRL_Wr = (Address == `ETH_TX_CTRL_ADR ) & Write;
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wire RXCTRL_Wr = (Address == `ETH_RX_CTRL_ADR ) & Write;
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wire RXCTRL_Wr = (Address == `ETH_RX_CTRL_ADR ) & Write;
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assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR ) & Write;
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assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR ) & Write & (DataIn<='h80);
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wire [31:0] MODEROut;
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wire [31:0] MODEROut;
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wire [31:0] INT_SOURCEOut;
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wire [31:0] INT_SOURCEOut;
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| Line 318... |
Line 322... |
wire [31:0] HASH0Out;
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wire [31:0] HASH0Out;
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wire [31:0] HASH1Out;
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wire [31:0] HASH1Out;
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wire [31:0] TXCTRLOut;
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wire [31:0] TXCTRLOut;
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wire [31:0] RXCTRLOut;
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wire [31:0] RXCTRLOut;
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// MODER Register
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// MODER Register
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eth_register #(`ETH_MODER_WIDTH, `ETH_MODER_DEF) MODER
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eth_register #(`ETH_MODER_WIDTH, `ETH_MODER_DEF) MODER
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(
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(
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.DataIn (DataIn[`ETH_MODER_WIDTH-1:0]),
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.DataIn (DataIn[`ETH_MODER_WIDTH-1:0]),
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.DataOut (MODEROut[`ETH_MODER_WIDTH-1:0]),
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.DataOut (MODEROut[`ETH_MODER_WIDTH-1:0]),
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| Line 418... |
Line 421... |
// TX_BD_NUM Register
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// TX_BD_NUM Register
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eth_register #(`ETH_TX_BD_NUM_WIDTH, `ETH_TX_BD_NUM_DEF) TX_BD_NUM
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eth_register #(`ETH_TX_BD_NUM_WIDTH, `ETH_TX_BD_NUM_DEF) TX_BD_NUM
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(
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(
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.DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH-1:0]),
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.DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH-1:0]),
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.DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH-1:0]),
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.DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH-1:0]),
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.Write (TX_BD_NUM_Wr & (DataIn<='h80)),
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.Write (TX_BD_NUM_Wr),
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.Clk (Clk),
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.Clk (Clk),
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.Reset (Reset),
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.Reset (Reset),
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.SyncReset (1'b0)
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.SyncReset (1'b0)
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);
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);
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assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH] = 0;
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assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH] = 0;
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