| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.26 2003/11/12 18:24:59 tadejm
|
|
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
|
|
//
|
// Revision 1.25 2003/04/18 16:26:25 mohor
|
// Revision 1.25 2003/04/18 16:26:25 mohor
|
// RxBDAddress was updated also when value to r_TxBDNum was written with
|
// RxBDAddress was updated also when value to r_TxBDNum was written with
|
// greater value than allowed.
|
// greater value than allowed.
|
//
|
//
|
// Revision 1.24 2002/11/22 01:57:06 mohor
|
// Revision 1.24 2002/11/22 01:57:06 mohor
|
| Line 278... |
Line 281... |
reg ResetRxCIrq_sync3;
|
reg ResetRxCIrq_sync3;
|
|
|
wire [3:0] Write = Cs & {4{Rw}};
|
wire [3:0] Write = Cs & {4{Rw}};
|
wire Read = (|Cs) & ~Rw;
|
wire Read = (|Cs) & ~Rw;
|
|
|
wire MODER_Wr = (Address == `ETH_MODER_ADR );
|
wire MODER_Sel = (Address == `ETH_MODER_ADR );
|
wire INT_SOURCE_Wr = (Address == `ETH_INT_SOURCE_ADR );
|
wire INT_SOURCE_Sel = (Address == `ETH_INT_SOURCE_ADR );
|
wire INT_MASK_Wr = (Address == `ETH_INT_MASK_ADR );
|
wire INT_MASK_Sel = (Address == `ETH_INT_MASK_ADR );
|
wire IPGT_Wr = (Address == `ETH_IPGT_ADR );
|
wire IPGT_Sel = (Address == `ETH_IPGT_ADR );
|
wire IPGR1_Wr = (Address == `ETH_IPGR1_ADR );
|
wire IPGR1_Sel = (Address == `ETH_IPGR1_ADR );
|
wire IPGR2_Wr = (Address == `ETH_IPGR2_ADR );
|
wire IPGR2_Sel = (Address == `ETH_IPGR2_ADR );
|
wire PACKETLEN_Wr = (Address == `ETH_PACKETLEN_ADR );
|
wire PACKETLEN_Sel = (Address == `ETH_PACKETLEN_ADR );
|
wire COLLCONF_Wr = (Address == `ETH_COLLCONF_ADR );
|
wire COLLCONF_Sel = (Address == `ETH_COLLCONF_ADR );
|
|
|
wire CTRLMODER_Wr = (Address == `ETH_CTRLMODER_ADR );
|
wire CTRLMODER_Sel = (Address == `ETH_CTRLMODER_ADR );
|
wire MIIMODER_Wr = (Address == `ETH_MIIMODER_ADR );
|
wire MIIMODER_Sel = (Address == `ETH_MIIMODER_ADR );
|
wire MIICOMMAND_Wr = (Address == `ETH_MIICOMMAND_ADR );
|
wire MIICOMMAND_Sel = (Address == `ETH_MIICOMMAND_ADR );
|
wire MIIADDRESS_Wr = (Address == `ETH_MIIADDRESS_ADR );
|
wire MIIADDRESS_Sel = (Address == `ETH_MIIADDRESS_ADR );
|
wire MIITX_DATA_Wr = (Address == `ETH_MIITX_DATA_ADR );
|
wire MIITX_DATA_Sel = (Address == `ETH_MIITX_DATA_ADR );
|
wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
|
wire MAC_ADDR0_Sel = (Address == `ETH_MAC_ADDR0_ADR );
|
wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR );
|
wire MAC_ADDR1_Sel = (Address == `ETH_MAC_ADDR1_ADR );
|
wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR );
|
wire HASH0_Sel = (Address == `ETH_HASH0_ADR );
|
wire HASH0_Wr = (Address == `ETH_HASH0_ADR );
|
wire HASH1_Sel = (Address == `ETH_HASH1_ADR );
|
wire HASH1_Wr = (Address == `ETH_HASH1_ADR );
|
wire TXCTRL_Sel = (Address == `ETH_TX_CTRL_ADR );
|
wire TXCTRL_Wr = (Address == `ETH_TX_CTRL_ADR );
|
wire RXCTRL_Sel = (Address == `ETH_RX_CTRL_ADR );
|
wire RXCTRL_Wr = (Address == `ETH_RX_CTRL_ADR );
|
wire TX_BD_NUM_Sel = (Address == `ETH_TX_BD_NUM_ADR );
|
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR ) & (DataIn<='h80);
|
|
|
|
|
wire [2:0] MODER_Wr;
|
|
wire [0:0] INT_SOURCE_Wr;
|
|
wire [0:0] INT_MASK_Wr;
|
|
wire [0:0] IPGT_Wr;
|
|
wire [0:0] IPGR1_Wr;
|
|
wire [0:0] IPGR2_Wr;
|
|
wire [3:0] PACKETLEN_Wr;
|
|
wire [2:0] COLLCONF_Wr;
|
|
wire [0:0] CTRLMODER_Wr;
|
|
wire [1:0] MIIMODER_Wr;
|
|
wire [0:0] MIICOMMAND_Wr;
|
|
wire [1:0] MIIADDRESS_Wr;
|
|
wire [1:0] MIITX_DATA_Wr;
|
|
wire MIIRX_DATA_Wr;
|
|
wire [3:0] MAC_ADDR0_Wr;
|
|
wire [1:0] MAC_ADDR1_Wr;
|
|
wire [3:0] HASH0_Wr;
|
|
wire [3:0] HASH1_Wr;
|
|
wire [2:0] TXCTRL_Wr;
|
|
wire [1:0] RXCTRL_Wr;
|
|
|
|
assign MODER_Wr[0] = Write[0] & MODER_Sel;
|
|
assign MODER_Wr[1] = Write[1] & MODER_Sel;
|
|
assign MODER_Wr[2] = Write[2] & MODER_Sel;
|
|
assign INT_SOURCE_Wr[0] = Write[0] & INT_SOURCE_Sel;
|
|
assign INT_MASK_Wr[0] = Write[0] & INT_MASK_Sel;
|
|
assign IPGT_Wr[0] = Write[0] & IPGT_Sel;
|
|
assign IPGR1_Wr[0] = Write[0] & IPGR1_Sel;
|
|
assign IPGR2_Wr[0] = Write[0] & IPGR2_Sel;
|
|
assign PACKETLEN_Wr[0] = Write[0] & PACKETLEN_Sel;
|
|
assign PACKETLEN_Wr[1] = Write[1] & PACKETLEN_Sel;
|
|
assign PACKETLEN_Wr[2] = Write[2] & PACKETLEN_Sel;
|
|
assign PACKETLEN_Wr[3] = Write[3] & PACKETLEN_Sel;
|
|
assign COLLCONF_Wr[0] = Write[0] & COLLCONF_Sel;
|
|
assign COLLCONF_Wr[1] = 1'b0; // Not used
|
|
assign COLLCONF_Wr[2] = Write[2] & COLLCONF_Sel;
|
|
|
|
assign CTRLMODER_Wr[0] = Write[0] & CTRLMODER_Sel;
|
|
assign MIIMODER_Wr[0] = Write[0] & MIIMODER_Sel;
|
|
assign MIIMODER_Wr[1] = Write[1] & MIIMODER_Sel;
|
|
assign MIICOMMAND_Wr[0] = Write[0] & MIICOMMAND_Sel;
|
|
assign MIIADDRESS_Wr[0] = Write[0] & MIIADDRESS_Sel;
|
|
assign MIIADDRESS_Wr[1] = Write[1] & MIIADDRESS_Sel;
|
|
assign MIITX_DATA_Wr[0] = Write[0] & MIITX_DATA_Sel;
|
|
assign MIITX_DATA_Wr[1] = Write[1] & MIITX_DATA_Sel;
|
|
assign MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
|
|
assign MAC_ADDR0_Wr[0] = Write[0] & MAC_ADDR0_Sel;
|
|
assign MAC_ADDR0_Wr[1] = Write[1] & MAC_ADDR0_Sel;
|
|
assign MAC_ADDR0_Wr[2] = Write[2] & MAC_ADDR0_Sel;
|
|
assign MAC_ADDR0_Wr[3] = Write[3] & MAC_ADDR0_Sel;
|
|
assign MAC_ADDR1_Wr[0] = Write[0] & MAC_ADDR1_Sel;
|
|
assign MAC_ADDR1_Wr[1] = Write[1] & MAC_ADDR1_Sel;
|
|
assign HASH0_Wr[0] = Write[0] & HASH0_Sel;
|
|
assign HASH0_Wr[1] = Write[1] & HASH0_Sel;
|
|
assign HASH0_Wr[2] = Write[2] & HASH0_Sel;
|
|
assign HASH0_Wr[3] = Write[3] & HASH0_Sel;
|
|
assign HASH1_Wr[0] = Write[0] & HASH1_Sel;
|
|
assign HASH1_Wr[1] = Write[1] & HASH1_Sel;
|
|
assign HASH1_Wr[2] = Write[2] & HASH1_Sel;
|
|
assign HASH1_Wr[3] = Write[3] & HASH1_Sel;
|
|
assign TXCTRL_Wr[0] = Write[0] & TXCTRL_Sel;
|
|
assign TXCTRL_Wr[1] = Write[1] & TXCTRL_Sel;
|
|
assign TXCTRL_Wr[2] = Write[2] & TXCTRL_Sel;
|
|
assign RXCTRL_Wr[0] = Write[0] & RXCTRL_Sel;
|
|
assign RXCTRL_Wr[1] = Write[1] & RXCTRL_Sel;
|
|
assign TX_BD_NUM_Wr = Write[0] & TX_BD_NUM_Sel & (DataIn<='h80);
|
|
|
|
|
|
|
wire [31:0] MODEROut;
|
wire [31:0] MODEROut;
|
wire [31:0] INT_SOURCEOut;
|
wire [31:0] INT_SOURCEOut;
|
| Line 331... |
Line 401... |
// MODER Register
|
// MODER Register
|
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0
|
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0
|
(
|
(
|
.DataIn (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
|
.DataIn (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
|
.DataOut (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]),
|
.DataOut (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]),
|
.Write (MODER_Wr & Write[0]),
|
.Write (MODER_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1) MODER_1
|
eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1) MODER_1
|
(
|
(
|
.DataIn (DataIn[`ETH_MODER_WIDTH_1 + 7:8]),
|
.DataIn (DataIn[`ETH_MODER_WIDTH_1 + 7:8]),
|
.DataOut (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]),
|
.DataOut (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]),
|
.Write (MODER_Wr & Write[1]),
|
.Write (MODER_Wr[1]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2) MODER_2
|
eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2) MODER_2
|
(
|
(
|
.DataIn (DataIn[`ETH_MODER_WIDTH_2 + 15:16]),
|
.DataIn (DataIn[`ETH_MODER_WIDTH_2 + 15:16]),
|
.DataOut (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]),
|
.DataOut (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]),
|
.Write (MODER_Wr & Write[2]),
|
.Write (MODER_Wr[2]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0;
|
assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0;
|
| Line 361... |
Line 431... |
// INT_MASK Register
|
// INT_MASK Register
|
eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0) INT_MASK_0
|
eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0) INT_MASK_0
|
(
|
(
|
.DataIn (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]),
|
.DataIn (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]),
|
.DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]),
|
.DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]),
|
.Write (INT_MASK_Wr & Write[0]),
|
.Write (INT_MASK_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0;
|
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0;
|
| Line 373... |
Line 443... |
// IPGT Register
|
// IPGT Register
|
eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0) IPGT_0
|
eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0) IPGT_0
|
(
|
(
|
.DataIn (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]),
|
.DataIn (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]),
|
.DataOut (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]),
|
.DataOut (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]),
|
.Write (IPGT_Wr & Write[0]),
|
.Write (IPGT_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0;
|
assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0;
|
| Line 385... |
Line 455... |
// IPGR1 Register
|
// IPGR1 Register
|
eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0) IPGR1_0
|
eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0) IPGR1_0
|
(
|
(
|
.DataIn (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]),
|
.DataIn (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]),
|
.DataOut (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]),
|
.DataOut (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]),
|
.Write (IPGR1_Wr & Write[0]),
|
.Write (IPGR1_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0;
|
assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0;
|
| Line 397... |
Line 467... |
// IPGR2 Register
|
// IPGR2 Register
|
eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0) IPGR2_0
|
eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0) IPGR2_0
|
(
|
(
|
.DataIn (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]),
|
.DataIn (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]),
|
.DataOut (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]),
|
.DataOut (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]),
|
.Write (IPGR2_Wr & Write[0]),
|
.Write (IPGR2_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0;
|
assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0;
|
| Line 409... |
Line 479... |
// PACKETLEN Register
|
// PACKETLEN Register
|
eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0
|
eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0
|
(
|
(
|
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
|
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
|
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
|
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
|
.Write (PACKETLEN_Wr & Write[0]),
|
.Write (PACKETLEN_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1
|
eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1
|
(
|
(
|
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
|
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
|
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
|
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
|
.Write (PACKETLEN_Wr & Write[1]),
|
.Write (PACKETLEN_Wr[1]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2
|
eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2
|
(
|
(
|
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
|
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
|
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
|
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
|
.Write (PACKETLEN_Wr & Write[2]),
|
.Write (PACKETLEN_Wr[2]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3
|
eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3
|
(
|
(
|
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
|
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
|
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
|
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
|
.Write (PACKETLEN_Wr & Write[3]),
|
.Write (PACKETLEN_Wr[3]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
|
|
// COLLCONF Register
|
// COLLCONF Register
|
eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0) COLLCONF_0
|
eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0) COLLCONF_0
|
(
|
(
|
.DataIn (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]),
|
.DataIn (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]),
|
.DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]),
|
.DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]),
|
.Write (COLLCONF_Wr & Write[0]),
|
.Write (COLLCONF_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2) COLLCONF_2
|
eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2) COLLCONF_2
|
(
|
(
|
.DataIn (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]),
|
.DataIn (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]),
|
.DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]),
|
.DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]),
|
.Write (COLLCONF_Wr & Write[2]),
|
.Write (COLLCONF_Wr[2]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0;
|
assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0;
|
| Line 469... |
Line 539... |
// TX_BD_NUM Register
|
// TX_BD_NUM Register
|
eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0
|
eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0
|
(
|
(
|
.DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
|
.DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
|
.DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
|
.DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
|
.Write (TX_BD_NUM_Wr & Write[0]),
|
.Write (TX_BD_NUM_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0;
|
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0;
|
| Line 481... |
Line 551... |
// CTRLMODER Register
|
// CTRLMODER Register
|
eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0) CTRLMODER_0
|
eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0) CTRLMODER_0
|
(
|
(
|
.DataIn (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
|
.DataIn (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
|
.DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
|
.DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
|
.Write (CTRLMODER_Wr & Write[0]),
|
.Write (CTRLMODER_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0;
|
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0;
|
| Line 493... |
Line 563... |
// MIIMODER Register
|
// MIIMODER Register
|
eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0) MIIMODER_0
|
eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0) MIIMODER_0
|
(
|
(
|
.DataIn (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]),
|
.DataIn (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]),
|
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]),
|
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]),
|
.Write (MIIMODER_Wr & Write[0]),
|
.Write (MIIMODER_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1) MIIMODER_1
|
eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1) MIIMODER_1
|
(
|
(
|
.DataIn (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]),
|
.DataIn (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]),
|
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]),
|
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]),
|
.Write (MIIMODER_Wr & Write[1]),
|
.Write (MIIMODER_Wr[1]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0;
|
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0;
|
| Line 514... |
Line 584... |
// MIICOMMAND Register
|
// MIICOMMAND Register
|
eth_register #(1, 0) MIICOMMAND0
|
eth_register #(1, 0) MIICOMMAND0
|
(
|
(
|
.DataIn (DataIn[0]),
|
.DataIn (DataIn[0]),
|
.DataOut (MIICOMMANDOut[0]),
|
.DataOut (MIICOMMANDOut[0]),
|
.Write (MIICOMMAND_Wr & Write[0]),
|
.Write (MIICOMMAND_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(1, 0) MIICOMMAND1
|
eth_register #(1, 0) MIICOMMAND1
|
(
|
(
|
.DataIn (DataIn[1]),
|
.DataIn (DataIn[1]),
|
.DataOut (MIICOMMANDOut[1]),
|
.DataOut (MIICOMMANDOut[1]),
|
.Write (MIICOMMAND_Wr & Write[0]),
|
.Write (MIICOMMAND_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (RStatStart)
|
.SyncReset (RStatStart)
|
);
|
);
|
eth_register #(1, 0) MIICOMMAND2
|
eth_register #(1, 0) MIICOMMAND2
|
(
|
(
|
.DataIn (DataIn[2]),
|
.DataIn (DataIn[2]),
|
.DataOut (MIICOMMANDOut[2]),
|
.DataOut (MIICOMMANDOut[2]),
|
.Write (MIICOMMAND_Wr & Write[0]),
|
.Write (MIICOMMAND_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (WCtrlDataStart)
|
.SyncReset (WCtrlDataStart)
|
);
|
);
|
assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0;
|
assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0;
|
| Line 544... |
Line 614... |
// MIIADDRESSRegister
|
// MIIADDRESSRegister
|
eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0
|
eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0
|
(
|
(
|
.DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
|
.DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
|
.DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
|
.DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
|
.Write (MIIADDRESS_Wr & Write[0]),
|
.Write (MIIADDRESS_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1
|
eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1
|
(
|
(
|
.DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
|
.DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
|
.DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
|
.DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
|
.Write (MIIADDRESS_Wr & Write[1]),
|
.Write (MIIADDRESS_Wr[1]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0;
|
assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0;
|
| Line 566... |
Line 636... |
// MIITX_DATA Register
|
// MIITX_DATA Register
|
eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0
|
eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0
|
(
|
(
|
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
|
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
|
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
|
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
|
.Write (MIITX_DATA_Wr & Write[0]),
|
.Write (MIITX_DATA_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1
|
eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1
|
(
|
(
|
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
|
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
|
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
|
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
|
.Write (MIITX_DATA_Wr & Write[1]),
|
.Write (MIITX_DATA_Wr[1]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0;
|
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0;
|
| Line 599... |
Line 669... |
// MAC_ADDR0 Register
|
// MAC_ADDR0 Register
|
eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0) MAC_ADDR0_0
|
eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0) MAC_ADDR0_0
|
(
|
(
|
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
|
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
|
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
|
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
|
.Write (MAC_ADDR0_Wr & Write[0]),
|
.Write (MAC_ADDR0_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1) MAC_ADDR0_1
|
eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1) MAC_ADDR0_1
|
(
|
(
|
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
|
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
|
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
|
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
|
.Write (MAC_ADDR0_Wr & Write[1]),
|
.Write (MAC_ADDR0_Wr[1]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2) MAC_ADDR0_2
|
eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2) MAC_ADDR0_2
|
(
|
(
|
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
|
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
|
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
|
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
|
.Write (MAC_ADDR0_Wr & Write[2]),
|
.Write (MAC_ADDR0_Wr[2]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3) MAC_ADDR0_3
|
eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3) MAC_ADDR0_3
|
(
|
(
|
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
|
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
|
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
|
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
|
.Write (MAC_ADDR0_Wr & Write[3]),
|
.Write (MAC_ADDR0_Wr[3]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
|
|
// MAC_ADDR1 Register
|
// MAC_ADDR1 Register
|
eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0) MAC_ADDR1_0
|
eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0) MAC_ADDR1_0
|
(
|
(
|
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
|
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
|
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
|
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
|
.Write (MAC_ADDR1_Wr & Write[0]),
|
.Write (MAC_ADDR1_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1) MAC_ADDR1_1
|
eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1) MAC_ADDR1_1
|
(
|
(
|
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
|
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
|
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
|
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
|
.Write (MAC_ADDR1_Wr & Write[1]),
|
.Write (MAC_ADDR1_Wr[1]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0;
|
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0;
|
| Line 658... |
Line 728... |
// RXHASH0 Register
|
// RXHASH0 Register
|
eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0) RXHASH0_0
|
eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0) RXHASH0_0
|
(
|
(
|
.DataIn (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]),
|
.DataIn (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]),
|
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]),
|
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]),
|
.Write (HASH0_Wr & Write[0]),
|
.Write (HASH0_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1) RXHASH0_1
|
eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1) RXHASH0_1
|
(
|
(
|
.DataIn (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]),
|
.DataIn (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]),
|
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]),
|
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]),
|
.Write (HASH0_Wr & Write[1]),
|
.Write (HASH0_Wr[1]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2) RXHASH0_2
|
eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2) RXHASH0_2
|
(
|
(
|
.DataIn (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]),
|
.DataIn (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]),
|
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]),
|
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]),
|
.Write (HASH0_Wr & Write[2]),
|
.Write (HASH0_Wr[2]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3) RXHASH0_3
|
eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3) RXHASH0_3
|
(
|
(
|
.DataIn (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]),
|
.DataIn (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]),
|
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]),
|
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]),
|
.Write (HASH0_Wr & Write[3]),
|
.Write (HASH0_Wr[3]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
|
|
// RXHASH1 Register
|
// RXHASH1 Register
|
eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0) RXHASH1_0
|
eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0) RXHASH1_0
|
(
|
(
|
.DataIn (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]),
|
.DataIn (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]),
|
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]),
|
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]),
|
.Write (HASH1_Wr & Write[0]),
|
.Write (HASH1_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1) RXHASH1_1
|
eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1) RXHASH1_1
|
(
|
(
|
.DataIn (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]),
|
.DataIn (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]),
|
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]),
|
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]),
|
.Write (HASH1_Wr & Write[1]),
|
.Write (HASH1_Wr[1]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2) RXHASH1_2
|
eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2) RXHASH1_2
|
(
|
(
|
.DataIn (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]),
|
.DataIn (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]),
|
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]),
|
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]),
|
.Write (HASH1_Wr & Write[2]),
|
.Write (HASH1_Wr[2]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3) RXHASH1_3
|
eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3) RXHASH1_3
|
(
|
(
|
.DataIn (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]),
|
.DataIn (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]),
|
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]),
|
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]),
|
.Write (HASH1_Wr & Write[3]),
|
.Write (HASH1_Wr[3]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
|
|
// TXCTRL Register
|
// TXCTRL Register
|
eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0) TXCTRL_0
|
eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0) TXCTRL_0
|
(
|
(
|
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
|
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
|
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
|
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
|
.Write (TXCTRL_Wr & Write[0]),
|
.Write (TXCTRL_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1) TXCTRL_1
|
eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1) TXCTRL_1
|
(
|
(
|
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
|
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
|
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
|
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
|
.Write (TXCTRL_Wr & Write[1]),
|
.Write (TXCTRL_Wr[1]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2) TXCTRL_2 // Request bit is synchronously reset
|
eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2) TXCTRL_2 // Request bit is synchronously reset
|
(
|
(
|
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
|
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
|
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
|
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
|
.Write (TXCTRL_Wr & Write[2]),
|
.Write (TXCTRL_Wr[2]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (RstTxPauseRq)
|
.SyncReset (RstTxPauseRq)
|
);
|
);
|
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
|
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
|
| Line 764... |
Line 834... |
// RXCTRL Register
|
// RXCTRL Register
|
eth_register #(`ETH_RX_CTRL_WIDTH_0, `ETH_RX_CTRL_DEF_0) RXCTRL_0
|
eth_register #(`ETH_RX_CTRL_WIDTH_0, `ETH_RX_CTRL_DEF_0) RXCTRL_0
|
(
|
(
|
.DataIn (DataIn[`ETH_RX_CTRL_WIDTH_0 - 1:0]),
|
.DataIn (DataIn[`ETH_RX_CTRL_WIDTH_0 - 1:0]),
|
.DataOut (RXCTRLOut[`ETH_RX_CTRL_WIDTH_0 - 1:0]),
|
.DataOut (RXCTRLOut[`ETH_RX_CTRL_WIDTH_0 - 1:0]),
|
.Write (RXCTRL_Wr & Write[0]),
|
.Write (RXCTRL_Wr[0]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
eth_register #(`ETH_RX_CTRL_WIDTH_1, `ETH_RX_CTRL_DEF_1) RXCTRL_1
|
eth_register #(`ETH_RX_CTRL_WIDTH_1, `ETH_RX_CTRL_DEF_1) RXCTRL_1
|
(
|
(
|
.DataIn (DataIn[`ETH_RX_CTRL_WIDTH_1 + 7:8]),
|
.DataIn (DataIn[`ETH_RX_CTRL_WIDTH_1 + 7:8]),
|
.DataOut (RXCTRLOut[`ETH_RX_CTRL_WIDTH_1 + 7:8]),
|
.DataOut (RXCTRLOut[`ETH_RX_CTRL_WIDTH_1 + 7:8]),
|
.Write (RXCTRL_Wr & Write[1]),
|
.Write (RXCTRL_Wr[1]),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign RXCTRLOut[31:`ETH_RX_CTRL_WIDTH_1 + 8] = 0;
|
assign RXCTRLOut[31:`ETH_RX_CTRL_WIDTH_1 + 8] = 0;
|
| Line 1030... |
Line 1100... |
irq_txb <= 1'b0;
|
irq_txb <= 1'b0;
|
else
|
else
|
if(TxB_IRQ)
|
if(TxB_IRQ)
|
irq_txb <= #Tp 1'b1;
|
irq_txb <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & Write[0] & DataIn[0])
|
if(INT_SOURCE_Wr[0] & DataIn[0])
|
irq_txb <= #Tp 1'b0;
|
irq_txb <= #Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
| Line 1042... |
Line 1112... |
irq_txe <= 1'b0;
|
irq_txe <= 1'b0;
|
else
|
else
|
if(TxE_IRQ)
|
if(TxE_IRQ)
|
irq_txe <= #Tp 1'b1;
|
irq_txe <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & Write[0] & DataIn[1])
|
if(INT_SOURCE_Wr[0] & DataIn[1])
|
irq_txe <= #Tp 1'b0;
|
irq_txe <= #Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
| Line 1054... |
Line 1124... |
irq_rxb <= 1'b0;
|
irq_rxb <= 1'b0;
|
else
|
else
|
if(RxB_IRQ)
|
if(RxB_IRQ)
|
irq_rxb <= #Tp 1'b1;
|
irq_rxb <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & Write[0] & DataIn[2])
|
if(INT_SOURCE_Wr[0] & DataIn[2])
|
irq_rxb <= #Tp 1'b0;
|
irq_rxb <= #Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
| Line 1066... |
Line 1136... |
irq_rxe <= 1'b0;
|
irq_rxe <= 1'b0;
|
else
|
else
|
if(RxE_IRQ)
|
if(RxE_IRQ)
|
irq_rxe <= #Tp 1'b1;
|
irq_rxe <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & Write[0] & DataIn[3])
|
if(INT_SOURCE_Wr[0] & DataIn[3])
|
irq_rxe <= #Tp 1'b0;
|
irq_rxe <= #Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
| Line 1078... |
Line 1148... |
irq_busy <= 1'b0;
|
irq_busy <= 1'b0;
|
else
|
else
|
if(Busy_IRQ)
|
if(Busy_IRQ)
|
irq_busy <= #Tp 1'b1;
|
irq_busy <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & Write[0] & DataIn[4])
|
if(INT_SOURCE_Wr[0] & DataIn[4])
|
irq_busy <= #Tp 1'b0;
|
irq_busy <= #Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
| Line 1090... |
Line 1160... |
irq_txc <= 1'b0;
|
irq_txc <= 1'b0;
|
else
|
else
|
if(SetTxCIrq)
|
if(SetTxCIrq)
|
irq_txc <= #Tp 1'b1;
|
irq_txc <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & Write[0] & DataIn[5])
|
if(INT_SOURCE_Wr[0] & DataIn[5])
|
irq_txc <= #Tp 1'b0;
|
irq_txc <= #Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
| Line 1102... |
Line 1172... |
irq_rxc <= 1'b0;
|
irq_rxc <= 1'b0;
|
else
|
else
|
if(SetRxCIrq)
|
if(SetRxCIrq)
|
irq_rxc <= #Tp 1'b1;
|
irq_rxc <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & Write[0] & DataIn[6])
|
if(INT_SOURCE_Wr[0] & DataIn[6])
|
irq_rxc <= #Tp 1'b0;
|
irq_rxc <= #Tp 1'b0;
|
end
|
end
|
|
|
// Generating interrupt signal
|
// Generating interrupt signal
|
assign int_o = irq_txb & INT_MASKOut[0] |
|
assign int_o = irq_txb & INT_MASKOut[0] |
|
