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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Diff between revs 346 and 352

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Rev 346 Rev 352
Line 179... Line 179... 
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o,
 
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o,
 
                      r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
 
                      r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
 
                      StartTxDone, TxClk, RxClk, SetPauseTimer
 
                      StartTxDone, TxClk, RxClk, SetPauseTimer
 
                    );
 
                    );
 
 
 
 
 
parameter Tp = 1;
 
 
 
 
 
 
 
input [31:0] DataIn;
 
input [31:0] DataIn;
 
input [7:0] Address;
 
input [7:0] Address;
 
 
 
 
 
input Rw;
 
input Rw;
 
input [3:0] Cs;
 
input [3:0] Cs;
Line 946... Line 944... 
 
 
 
 
// Synchronizing TxC Interrupt
 
// Synchronizing TxC Interrupt
 
always @ (posedge TxClk or posedge Reset)
 
always @ (posedge TxClk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    SetTxCIrq_txclk <=#Tp 1'b0;
 
    SetTxCIrq_txclk <= 1'b0;
 
  else
 
  else
 
  if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
 
  if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
 
    SetTxCIrq_txclk <=#Tp 1'b1;
 
    SetTxCIrq_txclk <= 1'b1;
 
  else
 
  else
 
  if(ResetTxCIrq_sync2)
 
  if(ResetTxCIrq_sync2)
 
    SetTxCIrq_txclk <=#Tp 1'b0;
 
    SetTxCIrq_txclk <= 1'b0;
 
end
 
end
 
 
 
 
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    SetTxCIrq_sync1 <=#Tp 1'b0;
 
    SetTxCIrq_sync1 <= 1'b0;
 
  else
 
  else
 
    SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk;
 
    SetTxCIrq_sync1 <= SetTxCIrq_txclk;
 
end
 
end
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    SetTxCIrq_sync2 <=#Tp 1'b0;
 
    SetTxCIrq_sync2 <= 1'b0;
 
  else
 
  else
 
    SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
 
    SetTxCIrq_sync2 <= SetTxCIrq_sync1;
 
end
 
end
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    SetTxCIrq_sync3 <=#Tp 1'b0;
 
    SetTxCIrq_sync3 <= 1'b0;
 
  else
 
  else
 
    SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2;
 
    SetTxCIrq_sync3 <= SetTxCIrq_sync2;
 
end
 
end
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    SetTxCIrq <=#Tp 1'b0;
 
    SetTxCIrq <= 1'b0;
 
  else
 
  else
 
    SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
 
    SetTxCIrq <= SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
 
end
 
end
 
 
 
 
 
always @ (posedge TxClk or posedge Reset)
 
always @ (posedge TxClk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    ResetTxCIrq_sync1 <=#Tp 1'b0;
 
    ResetTxCIrq_sync1 <= 1'b0;
 
  else
 
  else
 
    ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2;
 
    ResetTxCIrq_sync1 <= SetTxCIrq_sync2;
 
end
 
end
 
 
 
 
 
always @ (posedge TxClk or posedge Reset)
 
always @ (posedge TxClk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    ResetTxCIrq_sync2 <=#Tp 1'b0;
 
    ResetTxCIrq_sync2 <= 1'b0;
 
  else
 
  else
 
    ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
 
    ResetTxCIrq_sync2 <= SetTxCIrq_sync1;
 
end
 
end
 
 
 
 
 
 
 
 
 
// Synchronizing RxC Interrupt
 
// Synchronizing RxC Interrupt
 
always @ (posedge RxClk or posedge Reset)
 
always @ (posedge RxClk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    SetRxCIrq_rxclk <=#Tp 1'b0;
 
    SetRxCIrq_rxclk <= 1'b0;
 
  else
 
  else
 
  if(SetPauseTimer & r_RxFlow)
 
  if(SetPauseTimer & r_RxFlow)
 
    SetRxCIrq_rxclk <=#Tp 1'b1;
 
    SetRxCIrq_rxclk <= 1'b1;
 
  else
 
  else
 
  if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
 
  if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
 
    SetRxCIrq_rxclk <=#Tp 1'b0;
 
    SetRxCIrq_rxclk <= 1'b0;
 
end
 
end
 
 
 
 
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    SetRxCIrq_sync1 <=#Tp 1'b0;
 
    SetRxCIrq_sync1 <= 1'b0;
 
  else
 
  else
 
    SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk;
 
    SetRxCIrq_sync1 <= SetRxCIrq_rxclk;
 
end
 
end
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    SetRxCIrq_sync2 <=#Tp 1'b0;
 
    SetRxCIrq_sync2 <= 1'b0;
 
  else
 
  else
 
    SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;
 
    SetRxCIrq_sync2 <= SetRxCIrq_sync1;
 
end
 
end
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    SetRxCIrq_sync3 <=#Tp 1'b0;
 
    SetRxCIrq_sync3 <= 1'b0;
 
  else
 
  else
 
    SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2;
 
    SetRxCIrq_sync3 <= SetRxCIrq_sync2;
 
end
 
end
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    SetRxCIrq <=#Tp 1'b0;
 
    SetRxCIrq <= 1'b0;
 
  else
 
  else
 
    SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
 
    SetRxCIrq <= SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
 
end
 
end
 
 
 
 
 
always @ (posedge RxClk or posedge Reset)
 
always @ (posedge RxClk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    ResetRxCIrq_sync1 <=#Tp 1'b0;
 
    ResetRxCIrq_sync1 <= 1'b0;
 
  else
 
  else
 
    ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
 
    ResetRxCIrq_sync1 <= SetRxCIrq_sync2;
 
end
 
end
 
 
 
 
 
always @ (posedge RxClk or posedge Reset)
 
always @ (posedge RxClk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    ResetRxCIrq_sync2 <=#Tp 1'b0;
 
    ResetRxCIrq_sync2 <= 1'b0;
 
  else
 
  else
 
    ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1;
 
    ResetRxCIrq_sync2 <= ResetRxCIrq_sync1;
 
end
 
end
 
 
 
 
 
always @ (posedge RxClk or posedge Reset)
 
always @ (posedge RxClk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    ResetRxCIrq_sync3 <=#Tp 1'b0;
 
    ResetRxCIrq_sync3 <= 1'b0;
 
  else
 
  else
 
    ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2;
 
    ResetRxCIrq_sync3 <= ResetRxCIrq_sync2;
 
end
 
end
 
 
 
 
 
 
 
 
 
 
 
 
 
// Interrupt generation
 
// Interrupt generation
Line 1084... Line 1082... 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    irq_txb <= 1'b0;
 
    irq_txb <= 1'b0;
 
  else
 
  else
 
  if(TxB_IRQ)
 
  if(TxB_IRQ)
 
    irq_txb <= #Tp 1'b1;
 
    irq_txb <=  1'b1;
 
  else
 
  else
 
  if(INT_SOURCE_Wr[0] & DataIn[0])
 
  if(INT_SOURCE_Wr[0] & DataIn[0])
 
    irq_txb <= #Tp 1'b0;
 
    irq_txb <=  1'b0;
 
end
 
end
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    irq_txe <= 1'b0;
 
    irq_txe <= 1'b0;
 
  else
 
  else
 
  if(TxE_IRQ)
 
  if(TxE_IRQ)
 
    irq_txe <= #Tp 1'b1;
 
    irq_txe <=  1'b1;
 
  else
 
  else
 
  if(INT_SOURCE_Wr[0] & DataIn[1])
 
  if(INT_SOURCE_Wr[0] & DataIn[1])
 
    irq_txe <= #Tp 1'b0;
 
    irq_txe <=  1'b0;
 
end
 
end
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    irq_rxb <= 1'b0;
 
    irq_rxb <= 1'b0;
 
  else
 
  else
 
  if(RxB_IRQ)
 
  if(RxB_IRQ)
 
    irq_rxb <= #Tp 1'b1;
 
    irq_rxb <=  1'b1;
 
  else
 
  else
 
  if(INT_SOURCE_Wr[0] & DataIn[2])
 
  if(INT_SOURCE_Wr[0] & DataIn[2])
 
    irq_rxb <= #Tp 1'b0;
 
    irq_rxb <=  1'b0;
 
end
 
end
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    irq_rxe <= 1'b0;
 
    irq_rxe <= 1'b0;
 
  else
 
  else
 
  if(RxE_IRQ)
 
  if(RxE_IRQ)
 
    irq_rxe <= #Tp 1'b1;
 
    irq_rxe <=  1'b1;
 
  else
 
  else
 
  if(INT_SOURCE_Wr[0] & DataIn[3])
 
  if(INT_SOURCE_Wr[0] & DataIn[3])
 
    irq_rxe <= #Tp 1'b0;
 
    irq_rxe <=  1'b0;
 
end
 
end
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    irq_busy <= 1'b0;
 
    irq_busy <= 1'b0;
 
  else
 
  else
 
  if(Busy_IRQ)
 
  if(Busy_IRQ)
 
    irq_busy <= #Tp 1'b1;
 
    irq_busy <=  1'b1;
 
  else
 
  else
 
  if(INT_SOURCE_Wr[0] & DataIn[4])
 
  if(INT_SOURCE_Wr[0] & DataIn[4])
 
    irq_busy <= #Tp 1'b0;
 
    irq_busy <=  1'b0;
 
end
 
end
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    irq_txc <= 1'b0;
 
    irq_txc <= 1'b0;
 
  else
 
  else
 
  if(SetTxCIrq)
 
  if(SetTxCIrq)
 
    irq_txc <= #Tp 1'b1;
 
    irq_txc <=  1'b1;
 
  else
 
  else
 
  if(INT_SOURCE_Wr[0] & DataIn[5])
 
  if(INT_SOURCE_Wr[0] & DataIn[5])
 
    irq_txc <= #Tp 1'b0;
 
    irq_txc <=  1'b0;
 
end
 
end
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    irq_rxc <= 1'b0;
 
    irq_rxc <= 1'b0;
 
  else
 
  else
 
  if(SetRxCIrq)
 
  if(SetRxCIrq)
 
    irq_rxc <= #Tp 1'b1;
 
    irq_rxc <=  1'b1;
 
  else
 
  else
 
  if(INT_SOURCE_Wr[0] & DataIn[6])
 
  if(INT_SOURCE_Wr[0] & DataIn[6])
 
    irq_rxc <= #Tp 1'b0;
 
    irq_rxc <=  1'b0;
 
end
 
end
 
 
 
 
 
// Generating interrupt signal
 
// Generating interrupt signal
 
assign int_o = irq_txb  & INT_MASKOut[0] |
 
assign int_o = irq_txb  & INT_MASKOut[0] |
 
               irq_txe  & INT_MASKOut[1] |
 
               irq_txe  & INT_MASKOut[1] |

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