| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.12 2002/02/17 13:23:42 mohor
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// Define missmatch fixed.
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//
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// Revision 1.11 2002/02/16 14:03:44 mohor
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// Revision 1.11 2002/02/16 14:03:44 mohor
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// Registered trimmed. Unused registers removed.
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// Registered trimmed. Unused registers removed.
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//
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//
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// Revision 1.10 2002/02/15 11:08:25 mohor
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// Revision 1.10 2002/02/15 11:08:25 mohor
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// File format fixed a bit.
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// File format fixed a bit.
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| Line 106... |
Line 109... |
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module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
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module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
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r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
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r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
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r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
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r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
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r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
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r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, TxC_IRQ, RxC_IRQ,
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r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
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r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
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r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
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r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
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r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
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r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
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LinkFail, r_MAC, WCtrlDataStart, RStatStart,
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LinkFail, r_MAC, WCtrlDataStart, RStatStart,
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| Line 158... |
Line 161... |
output [31:0] r_HASH1;
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output [31:0] r_HASH1;
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input TxB_IRQ;
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input TxB_IRQ;
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input TxE_IRQ;
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input TxE_IRQ;
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input RxB_IRQ;
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input RxB_IRQ;
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input RxF_IRQ;
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input RxE_IRQ;
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input Busy_IRQ;
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input Busy_IRQ;
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input TxC_IRQ;
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input RxC_IRQ;
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output [6:0] r_IPGT;
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output [6:0] r_IPGT;
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output [6:0] r_IPGR1;
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output [6:0] r_IPGR1;
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| Line 203... |
Line 208... |
output int_o;
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output int_o;
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reg irq_txb;
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reg irq_txb;
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reg irq_txe;
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reg irq_txe;
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reg irq_rxb;
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reg irq_rxb;
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reg irq_rxf;
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reg irq_rxe;
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reg irq_busy;
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reg irq_busy;
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reg irq_txc;
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reg irq_rxc;
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wire Write = Cs & Rw;
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wire Write = Cs & Rw;
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wire Read = Cs & ~Rw;
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wire Read = Cs & ~Rw;
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wire MODER_Wr = (Address == `ETH_MODER_ADR ) & Write;
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wire MODER_Wr = (Address == `ETH_MODER_ADR ) & Write;
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| Line 255... |
Line 262... |
wire [31:0] TX_BD_NUMOut;
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wire [31:0] TX_BD_NUMOut;
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wire [31:0] HASH0Out;
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wire [31:0] HASH0Out;
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wire [31:0] HASH1Out;
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wire [31:0] HASH1Out;
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eth_register #(17, `ETH_MODER_DEF) MODER (.DataIn(DataIn[16:0]), .DataOut(MODEROut[16:0]), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset));
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eth_register #(17) MODER (.DataIn(DataIn[16:0]), .DataOut(MODEROut[16:0]), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
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assign MODEROut[31:17] = 0;
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assign MODEROut[31:17] = 0;
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eth_register #(5) INT_MASK (.DataIn(DataIn[4:0]), .DataOut(INT_MASKOut[4:0]), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
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eth_register #(7, `ETH_INT_MASK_DEF) INT_MASK (.DataIn(DataIn[6:0]), .DataOut(INT_MASKOut[6:0]), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset));
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assign INT_MASKOut[31:5] = 0;
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assign INT_MASKOut[31:7] = 0;
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eth_register #(7) IPGT (.DataIn(DataIn[6:0]), .DataOut(IPGTOut[6:0]), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
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eth_register #(7, `ETH_IPGT_DEF) IPGT (.DataIn(DataIn[6:0]), .DataOut(IPGTOut[6:0]), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset));
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assign IPGTOut[31:7] = 0;
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assign IPGTOut[31:7] = 0;
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eth_register #(7) IPGR1 (.DataIn(DataIn[6:0]), .DataOut(IPGR1Out[6:0]), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF));
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eth_register #(7, `ETH_IPGR1_DEF) IPGR1 (.DataIn(DataIn[6:0]), .DataOut(IPGR1Out[6:0]), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset));
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assign IPGR1Out[31:7] = 0;
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assign IPGR1Out[31:7] = 0;
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eth_register #(7) IPGR2 (.DataIn(DataIn[6:0]), .DataOut(IPGR2Out[6:0]), .Write(IPGR2_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR2_DEF));
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eth_register #(7, `ETH_IPGR2_DEF) IPGR2 (.DataIn(DataIn[6:0]), .DataOut(IPGR2Out[6:0]), .Write(IPGR2_Wr), .Clk(Clk), .Reset(Reset));
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assign IPGR2Out[31:7] = 0;
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assign IPGR2Out[31:7] = 0;
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eth_register #(32) PACKETLEN (.DataIn(DataIn), .DataOut(PACKETLENOut), .Write(PACKETLEN_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_PACKETLEN_DEF));
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eth_register #(32, `ETH_PACKETLEN_DEF) PACKETLEN (.DataIn(DataIn), .DataOut(PACKETLENOut), .Write(PACKETLEN_Wr), .Clk(Clk), .Reset(Reset));
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eth_register #(6) COLLCONF0 (.DataIn(DataIn[5:0]), .DataOut(COLLCONFOut[5:0]), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_COLLCONF0_DEF));
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eth_register #(6, `ETH_COLLCONF0_DEF) COLLCONF0 (.DataIn(DataIn[5:0]), .DataOut(COLLCONFOut[5:0]), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset));
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eth_register #(4) COLLCONF1 (.DataIn(DataIn[19:16]),.DataOut(COLLCONFOut[19:16]), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_COLLCONF1_DEF));
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eth_register #(4, `ETH_COLLCONF1_DEF) COLLCONF1 (.DataIn(DataIn[19:16]),.DataOut(COLLCONFOut[19:16]), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset));
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assign COLLCONFOut[15:6] = 0;
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assign COLLCONFOut[15:6] = 0;
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assign COLLCONFOut[31:20] = 0;
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assign COLLCONFOut[31:20] = 0;
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eth_register #(8) TX_BD_NUM (.DataIn(DataIn[7:0]), .DataOut(TX_BD_NUMOut[7:0]), .Write(TX_BD_NUM_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_TX_BD_NUM_DEF));
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eth_register #(8, `ETH_TX_BD_NUM_DEF) TX_BD_NUM (.DataIn(DataIn[7:0]), .DataOut(TX_BD_NUMOut[7:0]), .Write(TX_BD_NUM_Wr), .Clk(Clk), .Reset(Reset));
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assign TX_BD_NUMOut[31:8] = 24'h0;
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assign TX_BD_NUMOut[31:8] = 24'h0;
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eth_register #(3) CTRLMODER2 (.DataIn(DataIn[2:0]), .DataOut(CTRLMODEROut[2:0]), .Write(CTRLMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_CTRLMODER_DEF));
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eth_register #(3, `ETH_CTRLMODER_DEF) CTRLMODER2 (.DataIn(DataIn[2:0]), .DataOut(CTRLMODEROut[2:0]), .Write(CTRLMODER_Wr), .Clk(Clk), .Reset(Reset));
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assign CTRLMODEROut[31:3] = 29'h0;
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assign CTRLMODEROut[31:3] = 29'h0;
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eth_register #(11) MIIMODER (.DataIn(DataIn[10:0]), .DataOut(MIIMODEROut[10:0]), .Write(MIIMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIMODER_DEF));
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eth_register #(11, `ETH_MIIMODER_DEF) MIIMODER (.DataIn(DataIn[10:0]), .DataOut(MIIMODEROut[10:0]), .Write(MIIMODER_Wr), .Clk(Clk), .Reset(Reset));
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assign MIIMODEROut[31:11] = 0;
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assign MIIMODEROut[31:11] = 0;
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eth_register #(1) MIICOMMAND2 (.DataIn(DataIn[2]), .DataOut(MIICOMMANDOut[2]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | WCtrlDataStart), .Default(1'b0));
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eth_register #(1, 0) MIICOMMAND2 (.DataIn(DataIn[2]), .DataOut(MIICOMMANDOut[2]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | WCtrlDataStart));
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eth_register #(1) MIICOMMAND1 (.DataIn(DataIn[1]), .DataOut(MIICOMMANDOut[1]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | RStatStart), .Default(1'b0));
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eth_register #(1, 0) MIICOMMAND1 (.DataIn(DataIn[1]), .DataOut(MIICOMMANDOut[1]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | RStatStart));
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eth_register #(1) MIICOMMAND0 (.DataIn(DataIn[0]), .DataOut(MIICOMMANDOut[0]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset), .Default(1'b0));
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eth_register #(1, 0) MIICOMMAND0 (.DataIn(DataIn[0]), .DataOut(MIICOMMANDOut[0]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset));
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assign MIICOMMANDOut[31:3] = 29'h0;
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assign MIICOMMANDOut[31:3] = 29'h0;
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eth_register #(5) MIIADDRESS0 (.DataIn(DataIn[4:0]), .DataOut(MIIADDRESSOut[4:0]), .Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIADDRESS0_DEF));
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eth_register #(5, `ETH_MIIADDRESS0_DEF) MIIADDRESS0 (.DataIn(DataIn[4:0]), .DataOut(MIIADDRESSOut[4:0]), .Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset));
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eth_register #(5) MIIADDRESS1 (.DataIn(DataIn[12:8]), .DataOut(MIIADDRESSOut[12:8]),.Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIADDRESS1_DEF));
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eth_register #(5, `ETH_MIIADDRESS1_DEF) MIIADDRESS1 (.DataIn(DataIn[12:8]), .DataOut(MIIADDRESSOut[12:8]),.Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset));
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assign MIIADDRESSOut[7:5] = 0;
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assign MIIADDRESSOut[7:5] = 0;
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assign MIIADDRESSOut[31:13] = 0;
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assign MIIADDRESSOut[31:13] = 0;
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eth_register #(16) MIITX_DATA (.DataIn(DataIn[15:0]), .DataOut(MIITX_DATAOut[15:0]),.Write(MIITX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIITX_DATA_DEF));
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eth_register #(16, `ETH_MIITX_DATA_DEF) MIITX_DATA (.DataIn(DataIn[15:0]), .DataOut(MIITX_DATAOut[15:0]),.Write(MIITX_DATA_Wr), .Clk(Clk), .Reset(Reset));
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assign MIITX_DATAOut[31:16] = 0;
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assign MIITX_DATAOut[31:16] = 0;
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eth_register #(16) MIIRX_DATA (.DataIn(Prsd[15:0]), .DataOut(MIIRX_DATAOut[15:0]),.Write(MIIRX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIRX_DATA_DEF));
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eth_register #(16, `ETH_MIIRX_DATA_DEF) MIIRX_DATA (.DataIn(Prsd[15:0]), .DataOut(MIIRX_DATAOut[15:0]),.Write(MIIRX_DATA_Wr), .Clk(Clk), .Reset(Reset));
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assign MIIRX_DATAOut[31:16] = 0;
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assign MIIRX_DATAOut[31:16] = 0;
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eth_register #(32) MAC_ADDR0 (.DataIn(DataIn), .DataOut(MAC_ADDR0Out), .Write(MAC_ADDR0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR0_DEF));
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eth_register #(32, `ETH_MAC_ADDR0_DEF) MAC_ADDR0 (.DataIn(DataIn), .DataOut(MAC_ADDR0Out), .Write(MAC_ADDR0_Wr), .Clk(Clk), .Reset(Reset));
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eth_register #(16) MAC_ADDR1 (.DataIn(DataIn[15:0]), .DataOut(MAC_ADDR1Out[15:0]), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR1_DEF));
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eth_register #(16, `ETH_MAC_ADDR1_DEF) MAC_ADDR1 (.DataIn(DataIn[15:0]), .DataOut(MAC_ADDR1Out[15:0]), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset));
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assign MAC_ADDR1Out[31:16] = 0;
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assign MAC_ADDR1Out[31:16] = 0;
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eth_register #(32) RXHASH0 (.DataIn(DataIn), .DataOut(HASH0Out), .Write(HASH0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH0_DEF));
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eth_register #(32, `ETH_HASH0_DEF) RXHASH0 (.DataIn(DataIn), .DataOut(HASH0Out), .Write(HASH0_Wr), .Clk(Clk), .Reset(Reset));
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eth_register #(32) RXHASH1 (.DataIn(DataIn), .DataOut(HASH1Out), .Write(HASH1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH1_DEF));
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eth_register #(32, `ETH_HASH1_DEF) RXHASH1 (.DataIn(DataIn), .DataOut(HASH1Out), .Write(HASH1_Wr), .Clk(Clk), .Reset(Reset));
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reg LinkFailRegister;
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reg LinkFailRegister;
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wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
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wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
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reg ResetLinkFailRegister_q1;
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reg ResetLinkFailRegister_q1;
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| Line 476... |
Line 482... |
end
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end
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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irq_rxf <= 1'b0;
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irq_rxe <= 1'b0;
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else
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else
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if(RxF_IRQ & INT_MASKOut[3])
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if(RxE_IRQ & INT_MASKOut[3])
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irq_rxf <= #Tp 1'b1;
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irq_rxe <= #Tp 1'b1;
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else
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else
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if(INT_SOURCE_Wr & DataIn[3])
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if(INT_SOURCE_Wr & DataIn[3])
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irq_rxf <= #Tp 1'b0;
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irq_rxe <= #Tp 1'b0;
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end
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end
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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| Line 497... |
Line 503... |
else
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else
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if(INT_SOURCE_Wr & DataIn[4])
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if(INT_SOURCE_Wr & DataIn[4])
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irq_busy <= #Tp 1'b0;
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irq_busy <= #Tp 1'b0;
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end
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end
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always @ (posedge Clk or posedge Reset)
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begin
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if(Reset)
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irq_txc <= 1'b0;
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else
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if(TxC_IRQ & INT_MASKOut[5])
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irq_txc <= #Tp 1'b1;
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else
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if(INT_SOURCE_Wr & DataIn[5])
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irq_txc <= #Tp 1'b0;
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end
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always @ (posedge Clk or posedge Reset)
|
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begin
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if(Reset)
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irq_rxc <= 1'b0;
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else
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if(RxC_IRQ & INT_MASKOut[6])
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irq_rxc <= #Tp 1'b1;
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else
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if(INT_SOURCE_Wr & DataIn[6])
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irq_rxc <= #Tp 1'b0;
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end
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// Generating interrupt signal
|
// Generating interrupt signal
|
assign int_o = irq_txb | irq_txe | irq_rxb | irq_rxf | irq_busy;
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assign int_o = irq_txb | irq_txe | irq_rxb | irq_rxe | irq_busy | irq_txc | irq_rxc;
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// For reading interrupt status
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// For reading interrupt status
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assign INT_SOURCEOut = {28'h0, irq_busy, irq_rxf, irq_rxb, irq_txe, irq_txb};
|
assign INT_SOURCEOut = {26'h0, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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