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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// eth_rxaddrcheck.v ////
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//// eth_rxaddrcheck.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/cores/ethmac/ ////
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//// http://www.opencores.org/project,ethmac/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Bill Dittenhofer (billditt@aol.com) ////
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//// - Bill Dittenhofer (billditt@aol.com) ////
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//// - Olof Kindgren (olof@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// Copyright (C) 2011 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// 2011-07-06 Olof Kindgren <olof@opencores.org>
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// Reset AdressMiss when a new frame arrives. Otherwise it will report
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// the last value when a frame is less than seven bytes
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2002/11/19 17:34:52 mohor
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//
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// // Revision 1.8 2002/11/19 17:34:52 mohor
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// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
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// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
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// that a frame was received because of the promiscous mode.
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// that a frame was received because of the promiscous mode.
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//
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//
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// Revision 1.7 2002/09/04 18:41:06 mohor
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// Revision 1.7 2002/09/04 18:41:06 mohor
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// Bug when last byte of destination address was not checked fixed.
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// Bug when last byte of destination address was not checked fixed.
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`include "timescale.v"
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`include "timescale.v"
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module eth_rxaddrcheck(MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro,
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module eth_rxaddrcheck(MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro,
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ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
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ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
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ByteCntEq6, ByteCntEq7, HASH0, HASH1,
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ByteCntEq6, ByteCntEq7, HASH0, HASH1, ByteCntEq0,
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CrcHash, CrcHashGood, StateData, RxEndFrm,
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CrcHash, CrcHashGood, StateData, RxEndFrm,
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Multicast, MAC, RxAbort, AddressMiss, PassAll,
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Multicast, MAC, RxAbort, AddressMiss, PassAll,
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ControlFrmAddressOK
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ControlFrmAddressOK
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);
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);
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input Reset;
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input Reset;
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input [7:0] RxData;
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input [7:0] RxData;
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input Broadcast;
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input Broadcast;
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input r_Bro;
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input r_Bro;
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input r_Pro;
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input r_Pro;
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input ByteCntEq0;
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input ByteCntEq2;
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input ByteCntEq2;
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input ByteCntEq3;
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input ByteCntEq3;
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input ByteCntEq4;
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input ByteCntEq4;
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input ByteCntEq5;
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input ByteCntEq5;
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input ByteCntEq6;
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input ByteCntEq6;
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// This ff holds the "Address Miss" information that is written to the RX BD status.
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// This ff holds the "Address Miss" information that is written to the RX BD status.
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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AddressMiss <= #Tp 1'b0;
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AddressMiss <= #Tp 1'b0;
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else if(ByteCntEq0)
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AddressMiss <= #Tp 1'b0;
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else if(ByteCntEq7 & RxCheckEn)
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else if(ByteCntEq7 & RxCheckEn)
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AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
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AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
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end
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end
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