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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxaddrcheck.v] - Diff between revs 50 and 65

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Rev 50	Rev 65
Line 90...	Line 90...
`wire ByteCntEq3;`	`wire ByteCntEq3;`
`wire ByteCntEq4;`	`wire ByteCntEq4;`
`wire ByteCntEq5;`	`wire ByteCntEq5;`
`wire RxAddressInvalid;`	`wire RxAddressInvalid;`
`wire RxCheckEn;`	`wire RxCheckEn;`
`reg [31:0] IntHash;`	`wire HashBit;`
	`wire [31:0] IntHash;`
`reg [7:0] ByteHash;`	`reg [7:0] ByteHash;`
`reg MulticastOK;`	`reg MulticastOK;`
`reg UnicastOK;`	`reg UnicastOK;`
`reg RxAbort;`	`reg RxAbort;`
`reg CrcHashGood_d; // delay HashGood by one cycle`	`reg CrcHashGood_d; // delay HashGood by one cycle`
`reg HashBit;`

`assign RxAddressInvalid = ~(UnicastOK \| BroadcastOK \| MulticastOK);`	`assign RxAddressInvalid = ~(UnicastOK \| BroadcastOK \| MulticastOK);`

	`assign BroadcastOK = Broadcast;`
`assign BroadcastOK = (Broadcast & ~r_Bro ) \| r_Pro;`

`assign RxCheckEn = \| StateData;`	`assign RxCheckEn = \| StateData;`

`// Address Error Reported at end of address cycle`	`// Address Error Reported at end of address cycle`
`// RxAbort clears after one cycle`	`// RxAbort clears after one cycle`

`always @ (posedge MRxClk or posedge Reset)`	`always @ (posedge MRxClk or posedge Reset)`
`begin`	`begin`
`if(Reset)`	`if(Reset)`
`RxAbort <= #Tp 1'b0;`	`RxAbort <= #Tp 1'b0;`
`else if( CrcHashGood_d & RxAddressInvalid & RxCheckEn)`	`else if(CrcHashGood_d & RxAddressInvalid & ~r_Pro & RxCheckEn)`
`RxAbort <= #Tp 1'b1;`	`RxAbort <= #Tp 1'b1;`
`else`	`else`
`RxAbort <= #Tp 1'b0;`	`RxAbort <= #Tp 1'b0;`
`end`	`end`

Line 138...	Line 137...
`MulticastOK <= #Tp 1'b0;`	`MulticastOK <= #Tp 1'b0;`
`else if (RxEndFrm \| RxAbort)`	`else if (RxEndFrm \| RxAbort)`
`MulticastOK <= #Tp 1'b0;`	`MulticastOK <= #Tp 1'b0;`
`else if(CrcHashGood & Multicast)`	`else if(CrcHashGood & Multicast)`
`MulticastOK <= #Tp HashBit;`	`MulticastOK <= #Tp HashBit;`

`end`	`end`




`// Address Detection (unicast)`	`// Address Detection (unicast)`
`// start with ByteCntEq2 due to delay of addres from RxData`	`// start with ByteCntEq2 due to delay of addres from RxData`

`always @ (posedge MRxClk or posedge Reset)`	`always @ (posedge MRxClk or posedge Reset)`
`begin`	`begin`
`if(Reset)`	`if(Reset)`
`UnicastOK <= #Tp 1'b0;`	`UnicastOK <= #Tp 1'b0;`
`else`	`else`
Line 174...	Line 169...
`else`	`else`
`if(RxEndFrm \| RxAbort)`	`if(RxEndFrm \| RxAbort)`
`UnicastOK <= #Tp 1'b0;`	`UnicastOK <= #Tp 1'b0;`
`end`	`end`

`always@(HASH0 or HASH1 or CrcHash[5])`	`assign IntHash = (CrcHash[5])? HASH1 : HASH0;`
`begin`
`if (CrcHash[5])`
`IntHash = HASH1;`
`else`
`IntHash = HASH0;`

`end`

`always@(CrcHash or IntHash)`	`always@(CrcHash or IntHash)`
`begin`	`begin`
`case(CrcHash[4:3])`	`case(CrcHash[4:3])`
`2'b00: ByteHash = IntHash[7:0];`	`2'b00: ByteHash = IntHash[7:0];`
Line 193...	Line 181...
`2'b10: ByteHash = IntHash[23:16];`	`2'b10: ByteHash = IntHash[23:16];`
`2'b11: ByteHash = IntHash[31:24];`	`2'b11: ByteHash = IntHash[31:24];`
`endcase`	`endcase`
`end`	`end`

`always@(CrcHash or ByteHash)`	`assign HashBit = ByteHash[CrcHash[2:0]];`
`begin`
`case(CrcHash[2:0])`
`3'h0: HashBit = ByteHash[0];`
`3'h1: HashBit = ByteHash[1];`
`3'h2: HashBit = ByteHash[2];`
`3'h3: HashBit = ByteHash[3];`
`3'h4: HashBit = ByteHash[4];`
`3'h5: HashBit = ByteHash[5];`
`3'h6: HashBit = ByteHash[6];`
`3'h7: HashBit = ByteHash[7];`
`endcase`
`end`

`endmodule`	`endmodule`
`No newline at end of file`	`No newline at end of file`

`No newline at end of file`	`No newline at end of file`

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxaddrcheck.v] - Diff between revs 50 and 65