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https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxaddrcheck.v] - Diff between revs 85 and 93
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| Rev 85 |
Rev 93 |
| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/03/02 21:06:32 mohor
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// Log info was missing.
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//
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//
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//
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// Revision 1.1 2002/02/08 12:51:54 ditt
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// Revision 1.1 2002/02/08 12:51:54 ditt
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// Initial release of the ethernet addresscheck module.
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// Initial release of the ethernet addresscheck module.
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//
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//
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//
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//
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Line 103... |
reg MulticastOK;
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reg MulticastOK;
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reg UnicastOK;
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reg UnicastOK;
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reg RxAbort;
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reg RxAbort;
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reg CrcHashGood_d; // delay HashGood by one cycle
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reg CrcHashGood_d; // delay HashGood by one cycle
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assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK);
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assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro);
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assign BroadcastOK = Broadcast & ~r_Bro;
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assign BroadcastOK = Broadcast & ~r_Bro;
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assign RxCheckEn = | StateData;
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assign RxCheckEn = | StateData;
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Line 116... |
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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RxAbort <= #Tp 1'b0;
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RxAbort <= #Tp 1'b0;
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else if(CrcHashGood_d & RxAddressInvalid & ~r_Pro & RxCheckEn)
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else if(CrcHashGood_d & RxAddressInvalid & RxCheckEn)
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RxAbort <= #Tp 1'b1;
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RxAbort <= #Tp 1'b1;
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else
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else
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RxAbort <= #Tp 1'b0;
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RxAbort <= #Tp 1'b0;
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end
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end
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