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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/02/15 11:13:29 mohor
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// Format of the file changed a bit.
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//
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// Revision 1.4 2002/02/14 20:19:41 billditt
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// Revision 1.4 2002/02/14 20:19:41 billditt
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// Modified for Address Checking,
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// Modified for Address Checking,
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// addition of eth_addrcheck.v
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// addition of eth_addrcheck.v
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//
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//
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// Revision 1.3 2002/01/23 10:28:16 mohor
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// Revision 1.3 2002/01/23 10:28:16 mohor
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module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
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module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
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MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
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MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
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ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
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ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
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ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCnt
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ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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input MRxClk;
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input MRxClk;
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output ByteCntEq6; // Byte counter = 6
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output ByteCntEq6; // Byte counter = 6
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output ByteCntEq7; // Byte counter = 7
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output ByteCntEq7; // Byte counter = 7
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output ByteCntGreat2; // Byte counter > 2
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output ByteCntGreat2; // Byte counter > 2
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output ByteCntSmall7; // Byte counter < 7
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output ByteCntSmall7; // Byte counter < 7
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output ByteCntMaxFrame; // Byte counter = MaxFL
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output ByteCntMaxFrame; // Byte counter = MaxFL
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output [15:0] ByteCnt; // Byte counter
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output [15:0] ByteCntOut; // Byte counter
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wire ResetByteCounter;
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wire ResetByteCounter;
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wire IncrementByteCounter;
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wire IncrementByteCounter;
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wire ResetIFGCounter;
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wire ResetIFGCounter;
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wire IncrementIFGCounter;
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wire IncrementIFGCounter;
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reg [15:0] ByteCnt;
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reg [15:0] ByteCnt;
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reg [3:0] DlyCrcCnt;
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reg [3:0] DlyCrcCnt;
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reg [4:0] IFGCounter;
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reg [4:0] IFGCounter;
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wire [15:0] ByteCntDelayed;
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assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame);
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assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame);
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assign IncrementByteCounter = ~ResetByteCounter & MRxDV &
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assign IncrementByteCounter = ~ResetByteCounter & MRxDV &
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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ByteCnt[15:0] <= #Tp 11'h0;
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ByteCnt[15:0] <= #Tp 16'h0;
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else
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else
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begin
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begin
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if(ResetByteCounter)
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if(ResetByteCounter)
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ByteCnt[15:0] <= #Tp 11'h0;
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ByteCnt[15:0] <= #Tp 16'h0;
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else
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else
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if(IncrementByteCounter)
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if(IncrementByteCounter)
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ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
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ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
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end
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end
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end
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end
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assign ByteCntDelayed = ByteCnt + 3'h4;
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assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt;
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assign ByteCntEq0 = ByteCnt == 16'h0;
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assign ByteCntEq0 = ByteCnt == 16'h0;
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assign ByteCntEq1 = ByteCnt == 16'h1;
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assign ByteCntEq1 = ByteCnt == 16'h1;
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assign ByteCntEq2 = ByteCnt == 16'h2;
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assign ByteCntEq2 = ByteCnt == 16'h2;
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assign ByteCntEq3 = ByteCnt == 16'h3;
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assign ByteCntEq3 = ByteCnt == 16'h3;
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assign ByteCntEq4 = ByteCnt == 16'h4;
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assign ByteCntEq4 = ByteCnt == 16'h4;
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assign ByteCntSmall7 = ByteCnt < 16'h7;
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assign ByteCntSmall7 = ByteCnt < 16'h7;
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assign ByteCntMax = ByteCnt == 16'hffff;
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assign ByteCntMax = ByteCnt == 16'hffff;
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assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn;
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assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn;
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assign ResetIFGCounter = StateSFD & MRxDV & MRxDEqD | StateDrop;
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assign ResetIFGCounter = StateSFD & MRxDV & MRxDEqD | StateDrop;
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assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
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assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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