| Line 87... |
Line 87... |
MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
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MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
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ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
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ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
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ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
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ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
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);
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);
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parameter Tp = 1;
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input MRxClk;
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input MRxClk;
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input Reset;
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input Reset;
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input MRxDV;
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input MRxDV;
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input StateSFD;
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input StateSFD;
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input [1:0] StateData;
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input [1:0] StateData;
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| Line 144... |
Line 142... |
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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ByteCnt[15:0] <= #Tp 16'h0;
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ByteCnt[15:0] <= 16'h0;
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else
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else
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begin
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begin
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if(ResetByteCounter)
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if(ResetByteCounter)
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ByteCnt[15:0] <= #Tp 16'h0;
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ByteCnt[15:0] <= 16'h0;
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else
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else
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if(IncrementByteCounter)
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if(IncrementByteCounter)
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ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
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ByteCnt[15:0] <= ByteCnt[15:0] + 1'b1;
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end
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end
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end
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end
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assign ByteCntDelayed = ByteCnt + 3'h4;
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assign ByteCntDelayed = ByteCnt + 3'h4;
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assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt;
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assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt;
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| Line 179... |
Line 177... |
assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
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assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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IFGCounter[4:0] <= #Tp 5'h0;
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IFGCounter[4:0] <= 5'h0;
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else
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else
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begin
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begin
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if(ResetIFGCounter)
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if(ResetIFGCounter)
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IFGCounter[4:0] <= #Tp 5'h0;
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IFGCounter[4:0] <= 5'h0;
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else
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else
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if(IncrementIFGCounter)
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if(IncrementIFGCounter)
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IFGCounter[4:0] <= #Tp IFGCounter[4:0] + 1'b1;
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IFGCounter[4:0] <= IFGCounter[4:0] + 1'b1;
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end
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end
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end
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end
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| Line 198... |
Line 196... |
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|
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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DlyCrcCnt[3:0] <= #Tp 4'h0;
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DlyCrcCnt[3:0] <= 4'h0;
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else
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else
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begin
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begin
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if(DlyCrcCnt[3:0] == 4'h9)
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if(DlyCrcCnt[3:0] == 4'h9)
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DlyCrcCnt[3:0] <= #Tp 4'h0;
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DlyCrcCnt[3:0] <= 4'h0;
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else
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else
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if(DlyCrcEn & StateSFD)
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if(DlyCrcEn & StateSFD)
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DlyCrcCnt[3:0] <= #Tp 4'h1;
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DlyCrcCnt[3:0] <= 4'h1;
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else
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else
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if(DlyCrcEn & (|DlyCrcCnt[3:0]))
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if(DlyCrcEn & (|DlyCrcCnt[3:0]))
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DlyCrcCnt[3:0] <= #Tp DlyCrcCnt[3:0] + 1'b1;
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DlyCrcCnt[3:0] <= DlyCrcCnt[3:0] + 1'b1;
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end
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end
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end
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end
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endmodule
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endmodule
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