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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// eth_rxethmac.v ////
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//// eth_rxethmac.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects,ethmac/ ////
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//// http://www.opencores.org/project,ethmac ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
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//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
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//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
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//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
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//// All additional information is avaliable in the Readme.txt ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2011 Authors ////
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//// Copyright (C) 2001, 2011 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
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module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG,
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RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
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HugEn, DlyCrcEn, RxData, RxValid, RxStartFrm, RxEndFrm,
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ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
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ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame,
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MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
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CrcError, StateIdle, StatePreamble, StateSFD, StateData,
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MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss,
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PassAll, ControlFrmAddressOK
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);
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);
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input MRxClk;
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input MRxClk;
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input MRxDV;
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input MRxDV;
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input [3:0] MRxD;
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input [3:0] MRxD;
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input Transmitting;
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input Transmitting;
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input HugEn;
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input HugEn;
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assign MRxDEqD = MRxD == 4'hd;
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assign MRxDEqD = MRxD == 4'hd;
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assign MRxDEq5 = MRxD == 4'h5;
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assign MRxDEq5 = MRxD == 4'h5;
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// Rx State Machine module
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// Rx State Machine module
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eth_rxstatem
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eth_rxstatem rxstatem1
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rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
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(.MRxClk(MRxClk),
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.ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
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.Reset(Reset),
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.MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
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.MRxDV(MRxDV),
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.StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
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.ByteCntEq0(ByteCntEq0),
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.StateSFD(StateSFD), .StateDrop(StateDrop)
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.ByteCntGreat2(ByteCntGreat2),
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.Transmitting(Transmitting),
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.MRxDEq5(MRxDEq5),
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.MRxDEqD(MRxDEqD),
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.IFGCounterEq24(IFGCounterEq24),
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.ByteCntMaxFrame(ByteCntMaxFrame),
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.StateData(StateData),
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.StateIdle(StateIdle),
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.StatePreamble(StatePreamble),
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.StateSFD(StateSFD),
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.StateDrop(StateDrop)
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);
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);
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// Rx Counters module
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// Rx Counters module
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eth_rxcounters
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eth_rxcounters rxcounters1
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rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
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(.MRxClk(MRxClk),
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.StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
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.Reset(Reset),
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.StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
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.MRxDV(MRxDV),
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.DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
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.StateIdle(StateIdle),
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.HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
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.StateSFD(StateSFD),
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.ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
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.StateData(StateData),
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.ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
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.StateDrop(StateDrop),
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.ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
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.StatePreamble(StatePreamble),
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.ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
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.MRxDEqD(MRxDEqD),
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.DlyCrcEn(DlyCrcEn),
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.DlyCrcCnt(DlyCrcCnt),
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.Transmitting(Transmitting),
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.MaxFL(MaxFL),
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.r_IFG(r_IFG),
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.HugEn(HugEn),
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.IFGCounterEq24(IFGCounterEq24),
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.ByteCntEq0(ByteCntEq0),
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.ByteCntEq1(ByteCntEq1),
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.ByteCntEq2(ByteCntEq2),
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.ByteCntEq3(ByteCntEq3),
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.ByteCntEq4(ByteCntEq4),
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.ByteCntEq5(ByteCntEq5),
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.ByteCntEq6(ByteCntEq6),
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.ByteCntEq7(ByteCntEq7),
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.ByteCntGreat2(ByteCntGreat2),
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.ByteCntSmall7(ByteCntSmall7),
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.ByteCntMaxFrame(ByteCntMaxFrame),
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.ByteCntOut(ByteCnt)
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.ByteCntOut(ByteCnt)
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);
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);
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// Rx Address Check
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// Rx Address Check
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eth_rxaddrcheck
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eth_rxaddrcheck rxaddrcheck1
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rxaddrcheck1
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(.MRxClk(MRxClk),
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(.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData),
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.Reset( Reset),
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.Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro),
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.RxData(RxData),
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.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
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.Broadcast (Broadcast),
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.ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
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.r_Bro (r_Bro),
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.HASH0(r_HASH0), .HASH1(r_HASH1), .ByteCntEq0(ByteCntEq0),
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.r_Pro(r_Pro),
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.CrcHash(CrcHash), .CrcHashGood(CrcHashGood), .StateData(StateData),
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.ByteCntEq6(ByteCntEq6),
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.Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
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.ByteCntEq7(ByteCntEq7),
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.RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss), .PassAll(PassAll),
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.ByteCntEq2(ByteCntEq2),
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.ByteCntEq3(ByteCntEq3),
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.ByteCntEq4(ByteCntEq4),
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.ByteCntEq5(ByteCntEq5),
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.HASH0(r_HASH0),
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.HASH1(r_HASH1),
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.ByteCntEq0(ByteCntEq0),
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.CrcHash(CrcHash),
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.CrcHashGood(CrcHashGood),
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.StateData(StateData),
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.Multicast(Multicast),
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.MAC(MAC),
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.RxAbort(RxAbort),
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.RxEndFrm(RxEndFrm),
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.AddressMiss(AddressMiss),
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.PassAll(PassAll),
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.ControlFrmAddressOK(ControlFrmAddressOK)
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.ControlFrmAddressOK(ControlFrmAddressOK)
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);
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);
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assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
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assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
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assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
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assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) &
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DlyCrcCnt[3:0] < 4'h9;
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assign Data_Crc[0] = MRxD[3];
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assign Data_Crc[0] = MRxD[3];
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assign Data_Crc[1] = MRxD[2];
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assign Data_Crc[1] = MRxD[2];
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assign Data_Crc[2] = MRxD[1];
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assign Data_Crc[2] = MRxD[1];
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assign Data_Crc[3] = MRxD[0];
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assign Data_Crc[3] = MRxD[0];
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// Connecting module Crc
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// Connecting module Crc
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eth_crc
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eth_crc crcrx
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crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
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(.Clk(MRxClk),
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.Crc(Crc), .CrcError(CrcError)
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.Reset(Reset),
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.Data(Data_Crc),
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.Enable(Enable_Crc),
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.Initialize(Initialize_Crc),
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.Crc(Crc),
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.CrcError(CrcError)
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);
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);
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// Latching CRC for use in the hash table
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// Latching CRC for use in the hash table
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always @ (posedge MRxClk)
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always @ (posedge MRxClk)
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begin
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begin
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CrcHashGood <= StateData[0] & ByteCntEq6;
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CrcHashGood <= StateData[0] & ByteCntEq6;
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end
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end
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else
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else
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if(StateData[0] & ByteCntEq6)
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if(StateData[0] & ByteCntEq6)
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CrcHash[5:0] <= Crc[31:26];
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CrcHash[5:0] <= Crc[31:26];
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end
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end
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// Output byte stream
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// Output byte stream
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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begin
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begin
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Line 325... |
LatchedByte[7:0] <= 8'h0;
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LatchedByte[7:0] <= 8'h0;
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RxData[7:0] <= 8'h0;
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RxData[7:0] <= 8'h0;
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end
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end
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else
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else
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begin
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begin
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LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]}; // Latched byte
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// Latched byte
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LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]};
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DelayData <= StateData[0];
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DelayData <= StateData[0];
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if(GenerateRxValid)
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if(GenerateRxValid)
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RxData_d[7:0] <= LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state
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// Data goes through only in data state
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RxData_d[7:0] <= LatchedByte[7:0] & {8{|StateData}};
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else
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else
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if(~DelayData)
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if(~DelayData)
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RxData_d[7:0] <= 8'h0; // Delaying data to be valid for two cycles. Zero when not active.
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// Delaying data to be valid for two cycles.
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// Zero when not active.
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RxData_d[7:0] <= 8'h0;
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RxData[7:0] <= RxData_d[7:0]; // Output data byte
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RxData[7:0] <= RxData_d[7:0]; // Output data byte
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end
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end
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end
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end
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Line 393... |
RxValid <= RxValid_d;
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RxValid <= RxValid_d;
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end
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end
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end
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end
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assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
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assign GenerateRxStartFrm = StateData[0] &
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((ByteCntEq1 & ~DlyCrcEn) |
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((DlyCrcCnt == 4'h3) & DlyCrcEn));
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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begin
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begin
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Line 412... |
RxStartFrm <= RxStartFrm_d;
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RxStartFrm <= RxStartFrm_d;
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end
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end
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end
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end
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assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
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assign GenerateRxEndFrm = StateData[0] &
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(~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
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assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;
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assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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