URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_shiftreg.v] - Diff between revs 352 and 355
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 352 |
Rev 355 |
| Line 114... |
Line 114... |
begin
|
begin
|
if(MdcEn_n)
|
if(MdcEn_n)
|
begin
|
begin
|
if(|ByteSelect)
|
if(|ByteSelect)
|
begin
|
begin
|
|
/* verilator lint_off CASEINCOMPLETE */
|
case (ByteSelect[3:0]) // synopsys parallel_case full_case
|
case (ByteSelect[3:0]) // synopsys parallel_case full_case
|
4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
|
4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
|
4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
|
4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
|
4'h4 : ShiftReg[7:0] <= CtrlData[15:8];
|
4'h4 : ShiftReg[7:0] <= CtrlData[15:8];
|
4'h8 : ShiftReg[7:0] <= CtrlData[7:0];
|
4'h8 : ShiftReg[7:0] <= CtrlData[7:0];
|
endcase
|
endcase // case (ByteSelect[3:0])
|
|
/* verilator lint_on CASEINCOMPLETE */
|
end
|
end
|
else
|
else
|
begin
|
begin
|
ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
|
ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
|
if(LatchByte[0])
|
if(LatchByte[0])
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.