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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_shiftreg.v] - Diff between revs 37 and 84

Rev 37	Rev 84
Line 39...	Line 39...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2002/01/23 10:28:16 mohor`
	`// Link in the header changed.`
	`//`
`// Revision 1.2 2001/10/19 08:43:51 mohor`	`// Revision 1.2 2001/10/19 08:43:51 mohor`
`// eth_timescale.v changed to timescale.v This is done because of the`	`// eth_timescale.v changed to timescale.v This is done because of the`
`// simulation of the few cores in a one joined project.`	`// simulation of the few cores in a one joined project.`
`//`	`//`
`// Revision 1.1 2001/08/06 14:44:29 mohor`	`// Revision 1.1 2001/08/06 14:44:29 mohor`
Line 122...	Line 125...
`ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};`	`ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};`
`if(LatchByte[0])`	`if(LatchByte[0])`
`begin`	`begin`
`Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};`	`Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};`
`if(Rgad == 5'h01)`	`if(Rgad == 5'h01)`
`LinkFail <= #Tp ~ShiftReg[1]; // because of shifting`	`LinkFail <= #Tp ~ShiftReg[2]; // because of shifting`
`end`	`end`
`else`	`else`
`begin`	`begin`
`if(LatchByte[1])`	`if(LatchByte[1])`
`Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};`	`Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};`