| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/09/23 18:24:31 mohor
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// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
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//
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// Revision 1.1 2002/07/23 16:36:09 mohor
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// Revision 1.1 2002/07/23 16:36:09 mohor
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// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
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// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
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//
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//
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//
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//
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//
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//
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| Line 51... |
Line 54... |
`include "timescale.v"
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`include "timescale.v"
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module eth_spram_256x32(
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module eth_spram_256x32(
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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clk, rst, ce, we, oe, addr, di, do
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clk, rst, ce, we, oe, addr, di, do
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`ifdef ETH_BIST
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,trst, SO, SI, shift_DR, capture_DR, extest, tck
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`endif
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);
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);
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//
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//
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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//
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//
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| Line 66... |
Line 76... |
input [7:0] addr; // address bus inputs
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input [7:0] addr; // address bus inputs
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input [31:0] di; // input data bus
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input [31:0] di; // input data bus
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output [31:0] do; // output data bus
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output [31:0] do; // output data bus
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`ifdef ETH_BIST
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input trst;
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input shift_DR, capture_DR, tck, extest;
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input SI;
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output SO;
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`endif
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`ifdef ETH_XILINX_RAMB4
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`ifdef ETH_XILINX_RAMB4
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RAMB4_S16 ram0
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RAMB4_S16 ram0
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(
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(
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.DO (do[15:0]),
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.DO (do[15:0]),
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| Line 92... |
Line 109... |
.RST (rst)
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.RST (rst)
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);
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);
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`else // !ETH_XILINX_RAMB4
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`else // !ETH_XILINX_RAMB4
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`ifdef ETH_VIRTUAL_SILICON_RAM
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`ifdef ETH_VIRTUAL_SILICON_RAM
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`ifdef ETH_BIST
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vs_hdsp_256x32_bist ram0_bist
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`else
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vs_hdsp_256x32 ram0
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vs_hdsp_256x32 ram0
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`endif
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(
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(
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.CK (clk),
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.CK (clk),
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.CEN (!ce),
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.CEN (!ce),
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.WEN (!we),
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.WEN (!we),
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.OEN (!oe),
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.OEN (!oe),
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.ADR (addr),
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.ADR (addr),
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.DI (di),
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.DI (di),
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.DOUT (do)
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.DOUT (do)
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`ifdef ETH_BIST
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,
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// reset
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.trst (trst),
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// debug chain signals
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.SO (SO),
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.SI (SI),
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.shift_DR (shift_DR),
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.capture_DR(capture_DR),
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.extest (extest),
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.tck (tck)
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`endif
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);
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);
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`else // !ETH_VIRTUAL_SILICON_RAM
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`else // !ETH_VIRTUAL_SILICON_RAM
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//
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//
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