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Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Diff between revs 297 and 302

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Rev 297	Rev 302
Line 39...	Line 39...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.5 2003/08/14 16:42:58 simons`
	`// Artisan ram instance added.`
	`//`
`// Revision 1.4 2002/10/18 17:04:20 tadejm`	`// Revision 1.4 2002/10/18 17:04:20 tadejm`
`// Changed BIST scan signals.`	`// Changed BIST scan signals.`
`//`	`//`
`// Revision 1.3 2002/10/10 16:29:30 mohor`	`// Revision 1.3 2002/10/10 16:29:30 mohor`
`// BIST added.`	`// BIST added.`
Line 64...	Line 67...
`clk, rst, ce, we, oe, addr, di, do`	`clk, rst, ce, we, oe, addr, di, do`

`ifdef ETH_BIST	`ifdef ETH_BIST
`,`	`,`
`// debug chain signals`	`// debug chain signals`
`scanb_rst, // bist scan reset`	`mbist_si_i, // bist scan serial in`
`scanb_clk, // bist scan clock`	`mbist_so_o, // bist scan serial out`
`scanb_si, // bist scan serial in`	`mbist_ctrl_i // bist chain shift control`
`scanb_so, // bist scan serial out`
`scanb_en // bist scan shift enable`
`endif	`endif



`);`	`);`
Line 89...	Line 90...
`input [31:0] di; // input data bus`	`input [31:0] di; // input data bus`
`output [31:0] do; // output data bus`	`output [31:0] do; // output data bus`


`ifdef ETH_BIST	`ifdef ETH_BIST
`input scanb_rst; // bist scan reset`	`input mbist_si_i; // bist scan serial in`
`input scanb_clk; // bist scan clock`	`output mbist_so_o; // bist scan serial out`
`input scanb_si; // bist scan serial in`	input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`output scanb_so; // bist scan serial out`
`input scanb_en; // bist scan shift enable`
`endif	`endif

`ifdef ETH_XILINX_RAMB4	`ifdef ETH_XILINX_RAMB4

`RAMB4_S16 ram0`	`RAMB4_S16 ram0`
Line 139...	Line 138...
`.DOUT (do)`	`.DOUT (do)`

`ifdef ETH_BIST	`ifdef ETH_BIST
`,`	`,`
`// debug chain signals`	`// debug chain signals`
`.scanb_rst (scanb_rst),`	`.mbist_si_i (mbist_si_i),`
`.scanb_clk (scanb_clk),`	`.mbist_so_o (mbist_so_o),`
`.scanb_si (scanb_si),`	`.mbist_ctrl_i (mbist_ctrl_i)`
`.scanb_so (scanb_so),`
`.scanb_en (scanb_en)`
`endif	`endif
`);`	`);`

`else // !ETH_VIRTUAL_SILICON_RAM	`else // !ETH_VIRTUAL_SILICON_RAM

Line 167...	Line 164...
`.Q (do)`	`.Q (do)`

`ifdef ETH_BIST	`ifdef ETH_BIST
`,`	`,`
`// debug chain signals`	`// debug chain signals`
`.scanb_rst (scanb_rst),`	`.mbist_si_i (mbist_si_i),`
`.scanb_clk (scanb_clk),`	`.mbist_so_o (mbist_so_o),`
`.scanb_si (scanb_si),`	`.mbist_ctrl_i (mbist_ctrl_i)`
`.scanb_so (scanb_so),`
`.scanb_en (scanb_en)`
`endif	`endif
`);`	`);`

`else // !ETH_ARTISAN_RAM	`else // !ETH_ARTISAN_RAM
`//`	`//`

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Diff between revs 297 and 302