| Line 101... |
Line 101... |
ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
|
ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
|
LateCollision, DeferIndication, StatePreamble, StateData
|
LateCollision, DeferIndication, StatePreamble, StateData
|
|
|
);
|
);
|
|
|
parameter Tp = 1;
|
|
|
|
|
|
input MTxClk; // Transmit clock (from PHY)
|
input MTxClk; // Transmit clock (from PHY)
|
input Reset; // Reset
|
input Reset; // Reset
|
input TxStartFrm; // Transmit packet start frame
|
input TxStartFrm; // Transmit packet start frame
|
input TxEndFrm; // Transmit packet end frame
|
input TxEndFrm; // Transmit packet end frame
|
| Line 225... |
Line 223... |
|
|
// StopExcessiveDeferOccured
|
// StopExcessiveDeferOccured
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
StopExcessiveDeferOccured <= #Tp 1'b0;
|
StopExcessiveDeferOccured <= 1'b0;
|
else
|
else
|
begin
|
begin
|
if(~TxStartFrm)
|
if(~TxStartFrm)
|
StopExcessiveDeferOccured <= #Tp 1'b0;
|
StopExcessiveDeferOccured <= 1'b0;
|
else
|
else
|
if(ExcessiveDeferOccured)
|
if(ExcessiveDeferOccured)
|
StopExcessiveDeferOccured <= #Tp 1'b1;
|
StopExcessiveDeferOccured <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Collision Window
|
// Collision Window
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ColWindow <= #Tp 1'b1;
|
ColWindow <= 1'b1;
|
else
|
else
|
begin
|
begin
|
if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
|
if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
|
ColWindow <= #Tp 1'b0;
|
ColWindow <= 1'b0;
|
else
|
else
|
if(StateIdle | StateIPG)
|
if(StateIdle | StateIPG)
|
ColWindow <= #Tp 1'b1;
|
ColWindow <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Start Window
|
// Start Window
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
StatusLatch <= #Tp 1'b0;
|
StatusLatch <= 1'b0;
|
else
|
else
|
begin
|
begin
|
if(~TxStartFrm)
|
if(~TxStartFrm)
|
StatusLatch <= #Tp 1'b0;
|
StatusLatch <= 1'b0;
|
else
|
else
|
if(ExcessiveDeferOccured | StateIdle)
|
if(ExcessiveDeferOccured | StateIdle)
|
StatusLatch <= #Tp 1'b1;
|
StatusLatch <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Transmit packet used data
|
// Transmit packet used data
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxUsedData <= #Tp 1'b0;
|
TxUsedData <= 1'b0;
|
else
|
else
|
TxUsedData <= #Tp |StartData;
|
TxUsedData <= |StartData;
|
end
|
end
|
|
|
|
|
// Transmit packet done
|
// Transmit packet done
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxDone <= #Tp 1'b0;
|
TxDone <= 1'b0;
|
else
|
else
|
begin
|
begin
|
if(TxStartFrm & ~StatusLatch)
|
if(TxStartFrm & ~StatusLatch)
|
TxDone <= #Tp 1'b0;
|
TxDone <= 1'b0;
|
else
|
else
|
if(StartTxDone)
|
if(StartTxDone)
|
TxDone <= #Tp 1'b1;
|
TxDone <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Transmit packet retry
|
// Transmit packet retry
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxRetry <= #Tp 1'b0;
|
TxRetry <= 1'b0;
|
else
|
else
|
begin
|
begin
|
if(TxStartFrm & ~StatusLatch)
|
if(TxStartFrm & ~StatusLatch)
|
TxRetry <= #Tp 1'b0;
|
TxRetry <= 1'b0;
|
else
|
else
|
if(StartTxRetry)
|
if(StartTxRetry)
|
TxRetry <= #Tp 1'b1;
|
TxRetry <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Transmit packet abort
|
// Transmit packet abort
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxAbort <= #Tp 1'b0;
|
TxAbort <= 1'b0;
|
else
|
else
|
begin
|
begin
|
if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
|
if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
|
TxAbort <= #Tp 1'b0;
|
TxAbort <= 1'b0;
|
else
|
else
|
if(StartTxAbort)
|
if(StartTxAbort)
|
TxAbort <= #Tp 1'b1;
|
TxAbort <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Retry counter
|
// Retry counter
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RetryCnt[3:0] <= #Tp 4'h0;
|
RetryCnt[3:0] <= 4'h0;
|
else
|
else
|
begin
|
begin
|
if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
|
if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
|
| StateJam & NibCntEq7 & (~ColWindow | RetryMax))
|
| StateJam & NibCntEq7 & (~ColWindow | RetryMax))
|
RetryCnt[3:0] <= #Tp 4'h0;
|
RetryCnt[3:0] <= 4'h0;
|
else
|
else
|
if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
|
if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
|
RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1;
|
RetryCnt[3:0] <= RetryCnt[3:0] + 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
|
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
|
| Line 377... |
Line 375... |
|
|
// Transmit Enable
|
// Transmit Enable
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
MTxEn <= #Tp 1'b0;
|
MTxEn <= 1'b0;
|
else
|
else
|
MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
|
MTxEn <= StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
|
end
|
end
|
|
|
|
|
// Transmit nibble
|
// Transmit nibble
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
MTxD[3:0] <= #Tp 4'h0;
|
MTxD[3:0] <= 4'h0;
|
else
|
else
|
MTxD[3:0] <= #Tp MTxD_d[3:0];
|
MTxD[3:0] <= MTxD_d[3:0];
|
end
|
end
|
|
|
|
|
// Transmit error
|
// Transmit error
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
MTxErr <= #Tp 1'b0;
|
MTxErr <= 1'b0;
|
else
|
else
|
MTxErr <= #Tp TooBig | UnderRun;
|
MTxErr <= TooBig | UnderRun;
|
end
|
end
|
|
|
|
|
// WillTransmit
|
// WillTransmit
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
WillTransmit <= #Tp 1'b0;
|
WillTransmit <= 1'b0;
|
else
|
else
|
WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
|
WillTransmit <= StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
|
end
|
end
|
|
|
|
|
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
|
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
|
|
|
| Line 421... |
Line 419... |
// Packet finished
|
// Packet finished
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
PacketFinished <= #Tp 1'b0;
|
PacketFinished <= 1'b0;
|
PacketFinished_q <= #Tp 1'b0;
|
PacketFinished_q <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
PacketFinished <= #Tp PacketFinished_d;
|
PacketFinished <= PacketFinished_d;
|
PacketFinished_q <= #Tp PacketFinished;
|
PacketFinished_q <= PacketFinished;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Connecting module Counters
|
// Connecting module Counters
|
eth_txcounters #(.Tp(Tp))
|
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
|
txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
|
|
.StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
|
.StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
|
.StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
|
.StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
|
.StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
|
.StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
|
.Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
|
.Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
|
.PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
|
.PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
|
| Line 447... |
Line 444... |
.DlyCrcCnt(DlyCrcCnt)
|
.DlyCrcCnt(DlyCrcCnt)
|
);
|
);
|
|
|
|
|
// Connecting module StateM
|
// Connecting module StateM
|
eth_txstatem #(.Tp(Tp))
|
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
|
txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
|
|
.NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
|
.NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
|
.TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
|
.TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
|
.UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
|
.UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
|
.NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
|
.NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
|
.NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
|
.NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
|
| Line 477... |
Line 473... |
|
|
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
|
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
|
|
|
|
|
// Connecting module Crc
|
// Connecting module Crc
|
eth_crc #(.Tp(Tp))
|
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
|
txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
|
|
.Crc(Crc), .CrcError(CrcError)
|
.Crc(Crc), .CrcError(CrcError)
|
);
|
);
|
|
|
|
|
// Connecting module Random
|
// Connecting module Random
|
eth_random #(.Tp(Tp))
|
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
|
random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
|
|
.NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
|
.NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
|
|
|
|
|
|
|
|
|
