| Line 94... |
Line 94... |
StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
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StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
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StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
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StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
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StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG
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StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG
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);
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);
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|
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parameter Tp = 1;
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|
|
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input MTxClk;
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input MTxClk;
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input Reset;
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input Reset;
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input ExcessiveDefer;
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input ExcessiveDefer;
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input CarrierSense;
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input CarrierSense;
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input [6:0] NibCnt;
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input [6:0] NibCnt;
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| Line 195... |
Line 193... |
// Tx State Machine
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// Tx State Machine
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always @ (posedge MTxClk or posedge Reset)
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always @ (posedge MTxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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begin
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begin
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StateIPG <= #Tp 1'b0;
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StateIPG <= 1'b0;
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StateIdle <= #Tp 1'b0;
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StateIdle <= 1'b0;
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StatePreamble <= #Tp 1'b0;
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StatePreamble <= 1'b0;
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StateData[1:0] <= #Tp 2'b0;
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StateData[1:0] <= 2'b0;
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StatePAD <= #Tp 1'b0;
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StatePAD <= 1'b0;
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StateFCS <= #Tp 1'b0;
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StateFCS <= 1'b0;
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StateJam <= #Tp 1'b0;
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StateJam <= 1'b0;
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StateJam_q <= #Tp 1'b0;
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StateJam_q <= 1'b0;
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StateBackOff <= #Tp 1'b0;
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StateBackOff <= 1'b0;
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StateDefer <= #Tp 1'b1;
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StateDefer <= 1'b1;
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end
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end
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else
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else
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begin
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begin
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StateData[1:0] <= #Tp StartData[1:0];
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StateData[1:0] <= StartData[1:0];
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StateJam_q <= #Tp StateJam;
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StateJam_q <= StateJam;
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if(StartDefer | StartIdle)
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if(StartDefer | StartIdle)
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StateIPG <= #Tp 1'b0;
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StateIPG <= 1'b0;
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else
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else
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if(StartIPG)
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if(StartIPG)
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StateIPG <= #Tp 1'b1;
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StateIPG <= 1'b1;
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|
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if(StartDefer | StartPreamble)
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if(StartDefer | StartPreamble)
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StateIdle <= #Tp 1'b0;
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StateIdle <= 1'b0;
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else
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else
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if(StartIdle)
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if(StartIdle)
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StateIdle <= #Tp 1'b1;
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StateIdle <= 1'b1;
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|
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if(StartData[0] | StartJam)
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if(StartData[0] | StartJam)
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StatePreamble <= #Tp 1'b0;
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StatePreamble <= 1'b0;
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else
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else
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if(StartPreamble)
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if(StartPreamble)
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StatePreamble <= #Tp 1'b1;
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StatePreamble <= 1'b1;
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|
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if(StartFCS | StartJam)
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if(StartFCS | StartJam)
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StatePAD <= #Tp 1'b0;
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StatePAD <= 1'b0;
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else
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else
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if(StartPAD)
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if(StartPAD)
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StatePAD <= #Tp 1'b1;
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StatePAD <= 1'b1;
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|
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if(StartJam | StartDefer)
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if(StartJam | StartDefer)
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StateFCS <= #Tp 1'b0;
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StateFCS <= 1'b0;
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else
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else
|
if(StartFCS)
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if(StartFCS)
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StateFCS <= #Tp 1'b1;
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StateFCS <= 1'b1;
|
|
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if(StartBackoff | StartDefer)
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if(StartBackoff | StartDefer)
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StateJam <= #Tp 1'b0;
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StateJam <= 1'b0;
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else
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else
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if(StartJam)
|
if(StartJam)
|
StateJam <= #Tp 1'b1;
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StateJam <= 1'b1;
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|
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if(StartDefer)
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if(StartDefer)
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StateBackOff <= #Tp 1'b0;
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StateBackOff <= 1'b0;
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else
|
else
|
if(StartBackoff)
|
if(StartBackoff)
|
StateBackOff <= #Tp 1'b1;
|
StateBackOff <= 1'b1;
|
|
|
if(StartIPG)
|
if(StartIPG)
|
StateDefer <= #Tp 1'b0;
|
StateDefer <= 1'b0;
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else
|
else
|
if(StartDefer)
|
if(StartDefer)
|
StateDefer <= #Tp 1'b1;
|
StateDefer <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// This sections defines which interpack gap rule to use
|
// This sections defines which interpack gap rule to use
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
Rule1 <= #Tp 1'b0;
|
Rule1 <= 1'b0;
|
else
|
else
|
begin
|
begin
|
if(StateIdle | StateBackOff)
|
if(StateIdle | StateBackOff)
|
Rule1 <= #Tp 1'b0;
|
Rule1 <= 1'b0;
|
else
|
else
|
if(StatePreamble | FullD)
|
if(StatePreamble | FullD)
|
Rule1 <= #Tp 1'b1;
|
Rule1 <= 1'b1;
|
end
|
end
|
end
|
end
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|
