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https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 113 and 115
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| Rev 113 |
Rev 115 |
| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.27 2002/07/11 02:53:20 mohor
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// RxPointer bug fixed.
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//
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// Revision 1.26 2002/07/10 13:12:38 mohor
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// Revision 1.26 2002/07/10 13:12:38 mohor
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// Previous bug wasn't succesfully removed. Now fixed.
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// Previous bug wasn't succesfully removed. Now fixed.
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//
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//
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// Revision 1.25 2002/07/09 23:53:24 mohor
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// Revision 1.25 2002/07/09 23:53:24 mohor
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// Master state machine had a bug when switching from master write to
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// Master state machine had a bug when switching from master write to
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Line 1138... |
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// Latching Rx buffer descriptor address
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// Latching Rx buffer descriptor address
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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RxBDAddress <=#Tp 8'h0;
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RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF;
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else
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else
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if(TX_BD_NUM_Wr) // When r_TxBDNum is updated, RxBDAddress is also
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if(TX_BD_NUM_Wr) // When r_TxBDNum is updated, RxBDAddress is also
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RxBDAddress <=#Tp WB_DAT_I[7:0];
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RxBDAddress <=#Tp WB_DAT_I[7:0];
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else
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else
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if(RxStatusWrite)
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if(RxStatusWrite)
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