Line 6... |
Line 6... |
//// http://www.opencores.org/projects/ethmac/ ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// All additional information is available in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// Copyright (C) 2001, 2002 Authors ////
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Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.35 2002/09/10 10:35:23 mohor
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// Ethernet debug registers removed.
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//
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// Revision 1.34 2002/09/08 16:31:49 mohor
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// Revision 1.34 2002/09/08 16:31:49 mohor
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// Async reset for WB_ACK_O removed (when core was in reset, it was
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// Async reset for WB_ACK_O removed (when core was in reset, it was
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// impossible to access BDs).
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// impossible to access BDs).
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// RxPointers and TxPointers names changed to be more descriptive.
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// RxPointers and TxPointers names changed to be more descriptive.
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// TxUnderRun synchronized.
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// TxUnderRun synchronized.
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Line 289... |
Line 292... |
reg TxB_IRQ;
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reg TxB_IRQ;
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reg TxE_IRQ;
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reg TxE_IRQ;
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reg RxB_IRQ;
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reg RxB_IRQ;
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reg RxE_IRQ;
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reg RxE_IRQ;
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reg TxStartFrm;
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reg TxStartFrm;
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reg TxEndFrm;
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reg TxEndFrm;
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reg [7:0] TxData;
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reg [7:0] TxData;
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reg TxUnderRun;
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reg TxUnderRun;
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Line 320... |
Line 322... |
reg TxRetry_wb_q;
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reg TxRetry_wb_q;
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reg TxDone_wb_q2;
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reg TxDone_wb_q2;
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reg TxAbort_wb_q2;
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reg TxAbort_wb_q2;
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reg TxRetry_wb_q2;
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reg TxRetry_wb_q2;
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reg RxBDReady;
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reg RxBDReady;
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reg RxReady;
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reg TxBDReady;
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reg TxBDReady;
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reg RxBDRead;
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reg RxBDRead;
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wire RxStatusWrite;
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wire RxStatusWrite;
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Line 1521... |
Line 1524... |
always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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RxBDRead <=#Tp 1'b1;
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RxBDRead <=#Tp 1'b1;
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else
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else
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if(StartRxBDRead & ~RxBDReady)
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if(StartRxBDRead & ~RxReady)
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RxBDRead <=#Tp 1'b1;
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RxBDRead <=#Tp 1'b1;
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else
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else
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if(RxBDReady)
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if(RxBDReady)
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RxBDRead <=#Tp 1'b0;
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RxBDRead <=#Tp 1'b0;
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end
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end
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Line 1538... |
Line 1541... |
always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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RxBDReady <=#Tp 1'b0;
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RxBDReady <=#Tp 1'b0;
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else
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else
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if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
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if(RxPointerRead)
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RxBDReady <=#Tp 1'b0;
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RxBDReady <=#Tp 1'b0;
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else
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else
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if(RxEn & RxEn_q & RxBDRead)
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if(RxEn & RxEn_q & RxBDRead)
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RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
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RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
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end
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end
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Line 1557... |
Line 1560... |
if(RxEn & RxEn_q & RxBDRead)
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if(RxEn & RxEn_q & RxBDRead)
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RxStatus <=#Tp ram_do[14:13];
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RxStatus <=#Tp ram_do[14:13];
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end
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end
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// RxReady generation
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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RxReady <=#Tp 1'b0;
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else
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if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
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RxReady <=#Tp 1'b0;
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else
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if(RxEn & RxEn_q & RxPointerRead)
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RxReady <=#Tp 1'b1;
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end
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// Reading Rx BD pointer
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// Reading Rx BD pointer
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Line 1573... |
Line 1588... |
RxPointerRead <=#Tp 1'b0;
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RxPointerRead <=#Tp 1'b0;
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else
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else
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if(StartRxPointerRead)
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if(StartRxPointerRead)
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RxPointerRead <=#Tp 1'b1;
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RxPointerRead <=#Tp 1'b1;
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else
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else
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if(RxEn_q)
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if(RxEn & RxEn_q)
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RxPointerRead <=#Tp 1'b0;
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RxPointerRead <=#Tp 1'b0;
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end
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end
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//Latching Rx buffer pointer from buffer descriptor;
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//Latching Rx buffer pointer from buffer descriptor;
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Line 1622... |
Line 1637... |
always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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RxEn_needed <=#Tp 1'b0;
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RxEn_needed <=#Tp 1'b0;
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else
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else
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if(~RxBDReady & r_RxEn & WbEn & ~WbEn_q)
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if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
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RxEn_needed <=#Tp 1'b1;
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RxEn_needed <=#Tp 1'b1;
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else
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else
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if(RxPointerRead & RxEn & RxEn_q)
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if(RxPointerRead & RxEn & RxEn_q)
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RxEn_needed <=#Tp 1'b0;
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RxEn_needed <=#Tp 1'b0;
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end
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end
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Line 1672... |
Line 1687... |
LastByteIn <=#Tp 1'b0;
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LastByteIn <=#Tp 1'b0;
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else
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else
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if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
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if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
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LastByteIn <=#Tp 1'b0;
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LastByteIn <=#Tp 1'b0;
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else
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else
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if(RxValid & RxBDReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
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if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
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LastByteIn <=#Tp 1'b1;
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LastByteIn <=#Tp 1'b1;
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end
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end
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reg ShiftEnded_rck;
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reg ShiftEnded_rck;
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reg ShiftEndedSync1;
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reg ShiftEndedSync1;
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Line 1710... |
Line 1725... |
RxByteCnt <=#Tp 2'h0;
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RxByteCnt <=#Tp 2'h0;
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else
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else
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if(ShiftEnded_rck | RxAbort)
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if(ShiftEnded_rck | RxAbort)
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RxByteCnt <=#Tp 2'h0;
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RxByteCnt <=#Tp 2'h0;
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else
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else
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if(RxValid & RxStartFrm & RxBDReady)
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if(RxValid & RxStartFrm & RxReady)
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case(RxPointerLSB_rst) // synopsys parallel_case
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case(RxPointerLSB_rst) // synopsys parallel_case
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2'h0 : RxByteCnt <=#Tp 2'h1;
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2'h0 : RxByteCnt <=#Tp 2'h1;
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2'h1 : RxByteCnt <=#Tp 2'h2;
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2'h1 : RxByteCnt <=#Tp 2'h2;
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2'h2 : RxByteCnt <=#Tp 2'h3;
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2'h2 : RxByteCnt <=#Tp 2'h3;
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2'h3 : RxByteCnt <=#Tp 2'h0;
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2'h3 : RxByteCnt <=#Tp 2'h0;
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endcase
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endcase
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else
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else
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if(RxValid & RxEnableWindow & RxBDReady | LastByteIn)
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if(RxValid & RxEnableWindow & RxReady | LastByteIn)
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RxByteCnt <=#Tp RxByteCnt + 1'b1;
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RxByteCnt <=#Tp RxByteCnt + 1'b1;
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end
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end
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// Indicates how many bytes are valid within the last word
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// Indicates how many bytes are valid within the last word
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Line 1747... |
Line 1762... |
always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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RxDataLatched1 <=#Tp 24'h0;
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RxDataLatched1 <=#Tp 24'h0;
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else
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else
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if(RxValid & RxBDReady & ~LastByteIn)
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if(RxValid & RxReady & ~LastByteIn)
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if(RxStartFrm)
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if(RxStartFrm)
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begin
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begin
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case(RxPointerLSB_rst) // synopsys parallel_case
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case(RxPointerLSB_rst) // synopsys parallel_case
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2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
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2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
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2'h1: RxDataLatched1[23:16] <=#Tp RxData;
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2'h1: RxDataLatched1[23:16] <=#Tp RxData;
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Line 1795... |
Line 1810... |
reg WriteRxDataToFifoSync2;
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reg WriteRxDataToFifoSync2;
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reg WriteRxDataToFifoSync3;
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reg WriteRxDataToFifoSync3;
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// Indicating start of the reception process
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// Indicating start of the reception process
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assign SetWriteRxDataToFifo = (RxValid & RxBDReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) | (RxValid & RxBDReady & RxStartFrm & (&RxPointerLSB_rst)) | (ShiftWillEnd & LastByteIn & (&RxByteCnt));
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assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
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(RxValid & RxReady & RxStartFrm & (&RxPointerLSB_rst)) |
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(ShiftWillEnd & LastByteIn & (&RxByteCnt));
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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WriteRxDataToFifo <=#Tp 1'b0;
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WriteRxDataToFifo <=#Tp 1'b0;
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Line 2149... |
Line 2166... |
else
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else
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RxE_IRQ <=#Tp 1'b0;
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RxE_IRQ <=#Tp 1'b0;
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end
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end
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|
|
|
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assign Busy_IRQ = 1'b0;
|
// Busy Interrupt
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|
|
|
reg Busy_IRQ_rck;
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reg Busy_IRQ_sync1;
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reg Busy_IRQ_sync2;
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reg Busy_IRQ_sync3;
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reg Busy_IRQ_syncb1;
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reg Busy_IRQ_syncb2;
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|
|
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always @ (posedge MRxClk or posedge Reset)
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begin
|
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if(Reset)
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Busy_IRQ_rck <=#Tp 1'b0;
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else
|
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if(RxValid & RxStartFrm & ~RxReady)
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Busy_IRQ_rck <=#Tp 1'b1;
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|
else
|
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if(Busy_IRQ_syncb2)
|
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Busy_IRQ_rck <=#Tp 1'b0;
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|
end
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|
|
|
always @ (posedge WB_CLK_I)
|
|
begin
|
|
Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
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Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
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Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
|
|
end
|
|
|
|
always @ (posedge MRxClk)
|
|
begin
|
|
Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
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|
Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
|
|
end
|
|
|
|
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
|
|
|
|
|
|
|
// TX
|
// TX
|
// bit 15 ready
|
// bit 15 ready
|