| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.56 2004/04/30 10:30:00 igorm
|
|
// Accidently deleted line put back.
|
|
//
|
// Revision 1.55 2004/04/26 15:26:23 igorm
|
// Revision 1.55 2004/04/26 15:26:23 igorm
|
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
|
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
|
// previous update of the core.
|
// previous update of the core.
|
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
|
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
|
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
|
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
|
| Line 284... |
Line 287... |
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
|
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
|
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
|
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
|
ReceivedPauseFrm,
|
ReceivedPauseFrm,
|
|
|
// Tx Status
|
// Tx Status
|
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
|
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, CarrierSenseLost
|
|
|
// Bist
|
// Bist
|
`ifdef ETH_BIST
|
`ifdef ETH_BIST
|
,
|
,
|
// debug chain signals
|
// debug chain signals
|
| Line 315... |
Line 318... |
input WB_WE_I; // WISHBONE write enable input
|
input WB_WE_I; // WISHBONE write enable input
|
input [3:0] BDCs; // Buffer descriptors are selected
|
input [3:0] BDCs; // Buffer descriptors are selected
|
output WB_ACK_O; // WISHBONE acknowledge output
|
output WB_ACK_O; // WISHBONE acknowledge output
|
|
|
// WISHBONE master
|
// WISHBONE master
|
output [31:0] m_wb_adr_o; //
|
output [29:0] m_wb_adr_o; //
|
output [3:0] m_wb_sel_o; //
|
output [3:0] m_wb_sel_o; //
|
output m_wb_we_o; //
|
output m_wb_we_o; //
|
output [31:0] m_wb_dat_o; //
|
output [31:0] m_wb_dat_o; //
|
output m_wb_cyc_o; //
|
output m_wb_cyc_o; //
|
output m_wb_stb_o; //
|
output m_wb_stb_o; //
|
| Line 353... |
Line 356... |
// Tx Status signals
|
// Tx Status signals
|
input [3:0] RetryCntLatched; // Latched Retry Counter
|
input [3:0] RetryCntLatched; // Latched Retry Counter
|
input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
|
input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
|
input LateCollLatched; // Late collision occured
|
input LateCollLatched; // Late collision occured
|
input DeferLatched; // Defer indication (Frame was defered before sucessfully sent)
|
input DeferLatched; // Defer indication (Frame was defered before sucessfully sent)
|
|
output RstDeferLatched;
|
input CarrierSenseLost; // Carrier Sense was lost during the frame transmission
|
input CarrierSenseLost; // Carrier Sense was lost during the frame transmission
|
|
|
// Tx
|
// Tx
|
input MTxClk; // Transmit clock (from PHY)
|
input MTxClk; // Transmit clock (from PHY)
|
input TxUsedData; // Transmit packet used data
|
input TxUsedData; // Transmit packet used data
|
| Line 450... |
Line 454... |
reg BlockingTxStatusWrite;
|
reg BlockingTxStatusWrite;
|
reg BlockingTxBDRead;
|
reg BlockingTxBDRead;
|
|
|
reg Flop;
|
reg Flop;
|
|
|
reg [7:0] TxBDAddress;
|
reg [7:1] TxBDAddress;
|
reg [7:0] RxBDAddress;
|
reg [7:1] RxBDAddress;
|
|
|
reg TxRetrySync1;
|
reg TxRetrySync1;
|
reg TxAbortSync1;
|
reg TxAbortSync1;
|
reg TxDoneSync1;
|
reg TxDoneSync1;
|
|
|
| Line 500... |
Line 504... |
wire RxIRQEn;
|
wire RxIRQEn;
|
wire WrapRxStatusBit;
|
wire WrapRxStatusBit;
|
|
|
wire [1:0] TxValidBytes;
|
wire [1:0] TxValidBytes;
|
|
|
wire [7:0] TempTxBDAddress;
|
wire [7:1] TempTxBDAddress;
|
wire [7:0] TempRxBDAddress;
|
wire [7:1] TempRxBDAddress;
|
|
|
wire RxStatusWrite;
|
wire RxStatusWrite;
|
|
wire RxBufferFull;
|
|
wire RxBufferAlmostEmpty;
|
|
wire RxBufferEmpty;
|
|
|
reg WB_ACK_O;
|
reg WB_ACK_O;
|
|
|
wire [8:0] RxStatusIn;
|
wire [8:0] RxStatusIn;
|
reg [8:0] RxStatusInLatched;
|
reg [8:0] RxStatusInLatched;
|
| Line 535... |
Line 542... |
|
|
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
assign m_wb_bte_o = 2'b00; // Linear burst
|
assign m_wb_bte_o = 2'b00; // Linear burst
|
`endif
|
`endif
|
|
|
|
assign m_wb_stb_o = m_wb_cyc_o;
|
|
|
always @ (posedge WB_CLK_I)
|
always @ (posedge WB_CLK_I)
|
begin
|
begin
|
WB_ACK_O <=#Tp (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
|
WB_ACK_O <=#Tp (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
|
end
|
end
|
| Line 593... |
Line 601... |
5'b100_10, 5'b100_11 :
|
5'b100_10, 5'b100_11 :
|
begin
|
begin
|
WbEn <=#Tp 1'b0;
|
WbEn <=#Tp 1'b0;
|
RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled
|
RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled
|
TxEn <=#Tp 1'b0;
|
TxEn <=#Tp 1'b0;
|
ram_addr <=#Tp RxBDAddress + RxPointerRead;
|
ram_addr <=#Tp {RxBDAddress, RxPointerRead};
|
ram_di <=#Tp RxBDDataIn;
|
ram_di <=#Tp RxBDDataIn;
|
end
|
end
|
5'b100_01 :
|
5'b100_01 :
|
begin
|
begin
|
WbEn <=#Tp 1'b0;
|
WbEn <=#Tp 1'b0;
|
RxEn <=#Tp 1'b0;
|
RxEn <=#Tp 1'b0;
|
TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled
|
TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled
|
ram_addr <=#Tp TxBDAddress + TxPointerRead;
|
ram_addr <=#Tp {TxBDAddress, TxPointerRead};
|
ram_di <=#Tp TxBDDataIn;
|
ram_di <=#Tp TxBDDataIn;
|
end
|
end
|
5'b010_00, 5'b010_10 :
|
5'b010_00, 5'b010_10 :
|
begin
|
begin
|
WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled
|
WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled
|
| Line 619... |
Line 627... |
5'b010_01, 5'b010_11 :
|
5'b010_01, 5'b010_11 :
|
begin
|
begin
|
WbEn <=#Tp 1'b0;
|
WbEn <=#Tp 1'b0;
|
RxEn <=#Tp 1'b0;
|
RxEn <=#Tp 1'b0;
|
TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled
|
TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled
|
ram_addr <=#Tp TxBDAddress + TxPointerRead;
|
ram_addr <=#Tp {TxBDAddress, TxPointerRead};
|
ram_di <=#Tp TxBDDataIn;
|
ram_di <=#Tp TxBDDataIn;
|
end
|
end
|
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
|
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
|
begin
|
begin
|
WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage)
|
WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage)
|
| Line 756... |
Line 764... |
end
|
end
|
|
|
|
|
reg BlockingTxStatusWrite_sync1;
|
reg BlockingTxStatusWrite_sync1;
|
reg BlockingTxStatusWrite_sync2;
|
reg BlockingTxStatusWrite_sync2;
|
|
reg BlockingTxStatusWrite_sync3;
|
|
|
// Synchronizing BlockingTxStatusWrite to MTxClk
|
// Synchronizing BlockingTxStatusWrite to MTxClk
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 775... |
Line 784... |
BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
|
BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
|
else
|
else
|
BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
|
BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
|
end
|
end
|
|
|
|
// Synchronizing BlockingTxStatusWrite to MTxClk
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
BlockingTxStatusWrite_sync3 <=#Tp 1'b0;
|
|
else
|
|
BlockingTxStatusWrite_sync3 <=#Tp BlockingTxStatusWrite_sync2;
|
|
end
|
|
|
|
assign RstDeferLatched = BlockingTxStatusWrite_sync2 & ~BlockingTxStatusWrite_sync3;
|
|
|
// TxBDRead state is activated only once.
|
// TxBDRead state is activated only once.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 807... |
Line 826... |
wire WriteRxDataToMemory;
|
wire WriteRxDataToMemory;
|
|
|
reg MasterWbTX;
|
reg MasterWbTX;
|
reg MasterWbRX;
|
reg MasterWbRX;
|
|
|
reg [31:0] m_wb_adr_o;
|
reg [29:0] m_wb_adr_o;
|
reg m_wb_cyc_o;
|
reg m_wb_cyc_o;
|
reg m_wb_stb_o;
|
|
reg [3:0] m_wb_sel_o;
|
reg [3:0] m_wb_sel_o;
|
reg m_wb_we_o;
|
reg m_wb_we_o;
|
|
|
wire TxLengthEq0;
|
wire TxLengthEq0;
|
wire TxLengthLt4;
|
wire TxLengthLt4;
|
| Line 999... |
Line 1017... |
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b0;
|
MasterWbTX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_adr_o <=#Tp 32'h0;
|
m_wb_adr_o <=#Tp 30'h0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_sel_o <=#Tp 4'h0;
|
m_wb_sel_o <=#Tp 4'h0;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<=#Tp 1'b0;
|
tx_burst_cnt<=#Tp 0;
|
tx_burst_cnt<=#Tp 0;
|
rx_burst_cnt<=#Tp 0;
|
rx_burst_cnt<=#Tp 0;
|
| Line 1026... |
Line 1043... |
8'b01_1x_01_1x : // Clear (previously MW) and MRB needed
|
8'b01_1x_01_1x : // Clear (previously MW) and MRB needed
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b1; // tx burst
|
MasterWbTX <=#Tp 1'b1; // tx burst
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_sel_o <=#Tp 4'hf;
|
m_wb_sel_o <=#Tp 4'hf;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b1;
|
IncrTxPointer<=#Tp 1'b1;
|
tx_burst_cnt <=#Tp tx_burst_cnt+1;
|
tx_burst_cnt <=#Tp tx_burst_cnt+3'h1;
|
if(tx_burst_cnt==0)
|
if(tx_burst_cnt==0)
|
m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
|
m_wb_adr_o <=#Tp TxPointerMSB;
|
else
|
else
|
m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
|
m_wb_adr_o <=#Tp m_wb_adr_o+1'b1;
|
|
|
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
|
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
|
begin
|
begin
|
tx_burst_en<=#Tp 1'b0;
|
tx_burst_en<=#Tp 1'b0;
|
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
| Line 1059... |
Line 1075... |
8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed
|
8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b0; // rx burst
|
MasterWbTX <=#Tp 1'b0; // rx burst
|
MasterWbRX <=#Tp 1'b1;
|
MasterWbRX <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_sel_o <=#Tp RxByteSel;
|
m_wb_sel_o <=#Tp RxByteSel;
|
IncrTxPointer<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<=#Tp 1'b0;
|
rx_burst_cnt <=#Tp rx_burst_cnt+1;
|
rx_burst_cnt <=#Tp rx_burst_cnt+3'h1;
|
|
|
if(rx_burst_cnt==0)
|
if(rx_burst_cnt==0)
|
m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
|
m_wb_adr_o <=#Tp RxPointerMSB;
|
else
|
else
|
m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
|
m_wb_adr_o <=#Tp m_wb_adr_o+1'b1;
|
|
|
if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
|
if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
|
begin
|
begin
|
rx_burst_en<=#Tp 1'b0;
|
rx_burst_en<=#Tp 1'b0;
|
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
| Line 1089... |
Line 1104... |
end
|
end
|
8'b00_x1_00_x0 : // idle and MW is needed (data write to rx buffer)
|
8'b00_x1_00_x0 : // idle and MW is needed (data write to rx buffer)
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b0;
|
MasterWbTX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b1;
|
MasterWbRX <=#Tp 1'b1;
|
m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
|
m_wb_adr_o <=#Tp RxPointerMSB;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_sel_o <=#Tp RxByteSel;
|
m_wb_sel_o <=#Tp RxByteSel;
|
IncrTxPointer<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
end
|
end
|
8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer)
|
8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer)
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b1;
|
MasterWbTX <=#Tp 1'b1;
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
|
m_wb_adr_o <=#Tp TxPointerMSB;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_sel_o <=#Tp 4'hf;
|
m_wb_sel_o <=#Tp 4'hf;
|
IncrTxPointer<=#Tp 1'b1;
|
IncrTxPointer<=#Tp 1'b1;
|
end
|
end
|
8'b10_10_01_00, // MR and MR is needed (data read from tx buffer)
|
8'b10_10_01_00, // MR and MR is needed (data read from tx buffer)
|
8'b01_1x_01_0x : // MW and MR is needed (data read from tx buffer)
|
8'b01_1x_01_0x : // MW and MR is needed (data read from tx buffer)
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b1;
|
MasterWbTX <=#Tp 1'b1;
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
|
m_wb_adr_o <=#Tp TxPointerMSB;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_sel_o <=#Tp 4'hf;
|
m_wb_sel_o <=#Tp 4'hf;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b1;
|
IncrTxPointer<=#Tp 1'b1;
|
end
|
end
|
8'b01_01_01_00, // MW and MW needed (data write to rx buffer)
|
8'b01_01_01_00, // MW and MW needed (data write to rx buffer)
|
8'b10_x1_01_x0 : // MR and MW is needed (data write to rx buffer)
|
8'b10_x1_01_x0 : // MR and MW is needed (data write to rx buffer)
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b0;
|
MasterWbTX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b1;
|
MasterWbRX <=#Tp 1'b1;
|
m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
|
m_wb_adr_o <=#Tp RxPointerMSB;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_sel_o <=#Tp RxByteSel;
|
m_wb_sel_o <=#Tp RxByteSel;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
end
|
end
|
| Line 1139... |
Line 1150... |
8'b01_1x_10_x0, // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
|
8'b01_1x_10_x0, // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
|
8'b10_10_10_00, // MR and MR needed (cycle is cleared between previous and next access)
|
8'b10_10_10_00, // MR and MR needed (cycle is cleared between previous and next access)
|
8'b10_x1_10_0x : // MR and MR or MW or MWB (cycle is cleared between previous and next access)
|
8'b10_x1_10_0x : // MR and MR or MW or MWB (cycle is cleared between previous and next access)
|
begin
|
begin
|
m_wb_cyc_o <=#Tp 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
|
m_wb_cyc_o <=#Tp 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
|
m_wb_stb_o <=#Tp 1'b0;
|
|
cyc_cleared<=#Tp 1'b1;
|
cyc_cleared<=#Tp 1'b1;
|
IncrTxPointer<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
tx_burst_cnt<=#Tp 0;
|
tx_burst_cnt<=#Tp 0;
|
tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
|
tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
|
rx_burst_cnt<=#Tp 0;
|
rx_burst_cnt<=#Tp 0;
|
| Line 1156... |
Line 1166... |
8'bxx_00_01_00 : // Between cyc_cleared request was cleared
|
8'bxx_00_01_00 : // Between cyc_cleared request was cleared
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b0;
|
MasterWbTX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
rx_burst_cnt<=#Tp 0;
|
rx_burst_cnt<=#Tp 0;
|
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
|
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
|
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
| Line 1175... |
Line 1184... |
default: // Don't touch
|
default: // Don't touch
|
begin
|
begin
|
MasterWbTX <=#Tp MasterWbTX;
|
MasterWbTX <=#Tp MasterWbTX;
|
MasterWbRX <=#Tp MasterWbRX;
|
MasterWbRX <=#Tp MasterWbRX;
|
m_wb_cyc_o <=#Tp m_wb_cyc_o;
|
m_wb_cyc_o <=#Tp m_wb_cyc_o;
|
m_wb_stb_o <=#Tp m_wb_stb_o;
|
|
m_wb_sel_o <=#Tp m_wb_sel_o;
|
m_wb_sel_o <=#Tp m_wb_sel_o;
|
IncrTxPointer<=#Tp IncrTxPointer;
|
IncrTxPointer<=#Tp IncrTxPointer;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
| Line 1344... |
Line 1352... |
assign RxIRQEn = RxStatus[14];
|
assign RxIRQEn = RxStatus[14];
|
assign WrapRxStatusBit = RxStatus[13];
|
assign WrapRxStatusBit = RxStatus[13];
|
|
|
|
|
// Temporary Tx and Rx buffer descriptor address
|
// Temporary Tx and Rx buffer descriptor address
|
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
|
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD)
|
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1) | // Using first Rx BD
|
assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
|
{8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
|
{7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1) ; // Using next Rx BD (incremenrement address)
|
|
|
|
|
// Latching Tx buffer descriptor address
|
// Latching Tx buffer descriptor address
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxBDAddress <=#Tp 8'h0;
|
TxBDAddress <=#Tp 7'h0;
|
else if (r_TxEn & (~r_TxEn_q))
|
else if (r_TxEn & (~r_TxEn_q))
|
TxBDAddress <=#Tp 8'h0;
|
TxBDAddress <=#Tp 7'h0;
|
else if (TxStatusWrite)
|
else if (TxStatusWrite)
|
TxBDAddress <=#Tp TempTxBDAddress;
|
TxBDAddress <=#Tp TempTxBDAddress;
|
end
|
end
|
|
|
|
|
// Latching Rx buffer descriptor address
|
// Latching Rx buffer descriptor address
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxBDAddress <=#Tp 8'h0;
|
RxBDAddress <=#Tp 7'h0;
|
else if(r_RxEn & (~r_RxEn_q))
|
else if(r_RxEn & (~r_RxEn_q))
|
RxBDAddress <=#Tp r_TxBDNum << 1;
|
RxBDAddress <=#Tp r_TxBDNum[6:0];
|
else if(RxStatusWrite)
|
else if(RxStatusWrite)
|
RxBDAddress <=#Tp TempRxBDAddress;
|
RxBDAddress <=#Tp TempRxBDAddress;
|
end
|
end
|
|
|
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
|
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
|
| Line 1905... |
Line 1913... |
else
|
else
|
if(RxEn & RxEn_q & RxPointerRead)
|
if(RxEn & RxEn_q & RxPointerRead)
|
RxPointerMSB <=#Tp ram_do[31:2];
|
RxPointerMSB <=#Tp ram_do[31:2];
|
else
|
else
|
if(MasterWbRX & m_wb_ack_i)
|
if(MasterWbRX & m_wb_ack_i)
|
RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access (always word access. m_wb_sel_o are used for selecting bytes)
|
RxPointerMSB <=#Tp RxPointerMSB + 1'b1; // Word access (always word access. m_wb_sel_o are used for selecting bytes)
|
end
|
end
|
|
|
|
|
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
|
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
| Line 2027... |
Line 2035... |
2'h2 : RxValidBytes <=#Tp 2'h3;
|
2'h2 : RxValidBytes <=#Tp 2'h3;
|
2'h3 : RxValidBytes <=#Tp 2'h0;
|
2'h3 : RxValidBytes <=#Tp 2'h0;
|
endcase
|
endcase
|
else
|
else
|
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
|
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
|
RxValidBytes <=#Tp RxValidBytes + 1;
|
RxValidBytes <=#Tp RxValidBytes + 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
