| Line 307... |
Line 307... |
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
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parameter TX_FIFO_DEPTH = `ETH_TX_FIFO_DEPTH;
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parameter TX_FIFO_CNT_WIDTH = `ETH_TX_FIFO_CNT_WIDTH;
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parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
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parameter RX_FIFO_DEPTH = `ETH_RX_FIFO_DEPTH;
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parameter RX_FIFO_CNT_WIDTH = `ETH_RX_FIFO_CNT_WIDTH;
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// WISHBONE common
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// WISHBONE common
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input WB_CLK_I; // WISHBONE clock
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input WB_CLK_I; // WISHBONE clock
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input [31:0] WB_DAT_I; // WISHBONE data input
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input [31:0] WB_DAT_I; // WISHBONE data input
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| Line 1004... |
Line 1010... |
BlockReadTxDataFromMemory <=#Tp 1'b0;
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BlockReadTxDataFromMemory <=#Tp 1'b0;
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end
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end
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assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
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assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
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wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
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wire [TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
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wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
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wire [RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
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reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
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reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
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reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
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reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
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wire rx_burst;
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wire rx_burst;
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wire enough_data_in_rxfifo_for_burst;
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wire enough_data_in_rxfifo_for_burst;
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| Line 1156... |
Line 1162... |
begin
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begin
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m_wb_cyc_o <=#Tp 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
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m_wb_cyc_o <=#Tp 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
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cyc_cleared<=#Tp 1'b1;
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cyc_cleared<=#Tp 1'b1;
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IncrTxPointer<=#Tp 1'b0;
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IncrTxPointer<=#Tp 1'b0;
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tx_burst_cnt<=#Tp 0;
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tx_burst_cnt<=#Tp 0;
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tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
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tx_burst_en<=#Tp txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
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rx_burst_cnt<=#Tp 0;
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rx_burst_cnt<=#Tp 0;
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rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
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rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
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`ifdef ETH_WISHBONE_B3
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`ifdef ETH_WISHBONE_B3
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m_wb_cti_o <=#Tp 3'b0;
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m_wb_cti_o <=#Tp 3'b0;
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`endif
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`endif
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| Line 1180... |
Line 1186... |
`endif
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`endif
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end
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end
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8'b00_00_00_00: // whatever and no master read or write is needed (ack or err comes finishing previous access)
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8'b00_00_00_00: // whatever and no master read or write is needed (ack or err comes finishing previous access)
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begin
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begin
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tx_burst_cnt<=#Tp 0;
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tx_burst_cnt<=#Tp 0;
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tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
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tx_burst_en<=#Tp txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
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end
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end
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default: // Don't touch
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default: // Don't touch
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begin
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begin
|
MasterWbTX <=#Tp MasterWbTX;
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MasterWbTX <=#Tp MasterWbTX;
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MasterWbRX <=#Tp MasterWbRX;
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MasterWbRX <=#Tp MasterWbRX;
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| Line 1199... |
Line 1205... |
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wire TxFifoClear;
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wire TxFifoClear;
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|
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assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
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assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
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|
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eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
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eth_fifo #(.DATA_WIDTH(TX_FIFO_DATA_WIDTH),
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.DEPTH(TX_FIFO_DEPTH),
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.CNT_WIDTH(TX_FIFO_CNT_WIDTH),
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.Tp(Tp))
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tx_fifo ( .data_in(m_wb_dat_i), .data_out(TxData_wb),
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tx_fifo ( .data_in(m_wb_dat_i), .data_out(TxData_wb),
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.clk(WB_CLK_I), .reset(Reset),
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.clk(WB_CLK_I), .reset(Reset),
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.write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
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.write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
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.clear(TxFifoClear), .full(TxBufferFull),
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.clear(TxFifoClear), .full(TxBufferFull),
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.almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty),
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.almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty),
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| Line 2194... |
Line 2203... |
end
|
end
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|
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assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
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assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
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|
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eth_fifo #(.DATA_WIDTH(RX_FIFO_DATA_WIDTH),
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eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
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.DEPTH(RX_FIFO_DEPTH),
|
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.CNT_WIDTH(RX_FIFO_CNT_WIDTH),
|
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.Tp(Tp))
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rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
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rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
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.clk(WB_CLK_I), .reset(Reset),
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.clk(WB_CLK_I), .reset(Reset),
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.write(WriteRxDataToFifo_wb & ~RxBufferFull), .read(MasterWbRX & m_wb_ack_i),
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.write(WriteRxDataToFifo_wb & ~RxBufferFull), .read(MasterWbRX & m_wb_ack_i),
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.clear(RxFifoReset), .full(RxBufferFull),
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.clear(RxFifoReset), .full(RxBufferFull),
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.almost_full(), .almost_empty(RxBufferAlmostEmpty),
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.almost_full(), .almost_empty(RxBufferAlmostEmpty),
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