| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/05 16:44:39 mohor
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// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
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// MHz. Statuses, overrun, control frame transmission and reception still need
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// to be fixed.
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//
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// Revision 1.2 2002/02/01 12:46:51 mohor
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// Revision 1.2 2002/02/01 12:46:51 mohor
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// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
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// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
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// added.
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// added.
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//
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//
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// Revision 1.1 2002/01/23 10:47:59 mohor
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// Revision 1.1 2002/01/23 10:47:59 mohor
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| Line 325... |
Line 330... |
assign WB_ACK_O = temp_ack;
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assign WB_ACK_O = temp_ack;
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assign WB_DAT_O = ram_do;
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assign WB_DAT_O = ram_do;
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`endif
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`endif
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// Generic synchronous single-port RAM interface
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generic_spram #(8, 32) ram (
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// Generic synchronous single-port RAM interface
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.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
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);
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// Generic synchronous two-port RAM interface
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/*
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generic_tpram #(8, 32) i_generic_tpram
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(
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.clk_a(WB_CLK_I), .rst_a(Reset), .ce_a(1'b1), .we_a(BDWrite),
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.oe_a(EnableRAM), .addr_a(WB_ADR_I[9:2]), .di_a(WB_DAT_I), .do_a(WB_BDDataOut),
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.clk_b(WB_CLK_I), .rst_b(Reset), .ce_b(EnableRAM), .we_b(BDStatusWrite),
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.oe_b(EnableRAM), .addr_b(BDAddress[7:0]), .di_b(BDDataIn), .do_b(BDDataOut)
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);
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*/
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RAMB4_S16 ram1 (.DO(ram_do[15:0]), .ADDR(ram_addr), .DI(ram_di[15:0]), .EN(ram_ce),
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.CLK(WB_CLK_I), .WE(ram_we), .RST(Reset));
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RAMB4_S16 ram2 (.DO(ram_do[31:16]), .ADDR(ram_addr), .DI(ram_di[31:16]), .EN(ram_ce),
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.CLK(WB_CLK_I), .WE(ram_we), .RST(Reset));
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/*
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generic_spram #(8, 32) ram (
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// Generic synchronous single-port RAM interface
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.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
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);
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*/
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assign ram_ce = 1'b1;
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assign ram_ce = 1'b1;
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assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
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assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
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assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead); // Tu manjka se read kadar se bere RxBD
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assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead); // Tu manjka se read kadar se bere RxBD
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| Line 1557... |
Line 1539... |
end
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end
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wire WriteRxDataToFifo_wb;
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wire WriteRxDataToFifo_wb;
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assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync1 & ~WriteRxDataToFifoSync2;
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assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync1 & ~WriteRxDataToFifoSync2;
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reg RxAbortLatched;
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reg RxAbortSync1;
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reg RxAbortSync1;
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reg RxAbortSync2;
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reg RxAbortSync2;
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reg RxAbortSyncb1;
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reg RxAbortSyncb1;
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reg RxAbortSyncb2;
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reg RxAbortSyncb2;
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| Line 1636... |
Line 1617... |
if(RxEndFrm | RxAbort)
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if(RxEndFrm | RxAbort)
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RxEnableWindow <=#Tp 1'b0;
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RxEnableWindow <=#Tp 1'b0;
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end
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end
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// Generation of the end-of-frame signal
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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RxAbortLatched <=#Tp 1'b0;
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else
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if(RxAbort)
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RxAbortLatched <=#Tp 1'b1;
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else
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if(RxAbortSyncb2 | RxStartFrm)
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RxAbortLatched <=#Tp 1'b0;
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end
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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RxAbortSync1 <=#Tp 1'b0;
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RxAbortSync1 <=#Tp 1'b0;
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else
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else
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