| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2002/02/15 11:59:10 mohor
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// Changes that were lost when updating from 1.5 to 1.8 fixed.
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//
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// Revision 1.8 2002/02/14 20:54:33 billditt
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// Revision 1.8 2002/02/14 20:54:33 billditt
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// Addition of new module eth_addrcheck.v
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// Addition of new module eth_addrcheck.v
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//
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//
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// Revision 1.7 2002/02/12 17:03:47 mohor
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// Revision 1.7 2002/02/12 17:03:47 mohor
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// RxOverRun added to statuses.
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// RxOverRun added to statuses.
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| Line 372... |
Line 375... |
.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
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.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
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);
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);
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assign ram_ce = 1'b1;
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assign ram_ce = 1'b1;
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assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
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assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
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assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead); // Tu manjka se read kadar se bere RxBD
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assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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| Line 887... |
Line 890... |
begin
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begin
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if(Reset)
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if(Reset)
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TxStartFrm <=#Tp 1'b0;
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TxStartFrm <=#Tp 1'b0;
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else
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else
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if(TxStartFrm_sync2)
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if(TxStartFrm_sync2)
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TxStartFrm <=#Tp 1'b1; // igor !!! Dodaj se pogoj, da ni vmes prisel kaksen abort ali kaj podobnega
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TxStartFrm <=#Tp 1'b1;
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else
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else
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if(TxUsedData_q)
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if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry | TxAbort))
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TxStartFrm <=#Tp 1'b0;
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TxStartFrm <=#Tp 1'b0;
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end
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end
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// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
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// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
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| Line 1311... |
Line 1314... |
RxBDReady <=#Tp 1'b0;
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RxBDReady <=#Tp 1'b0;
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else
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else
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if(RxEn & RxEn_q & RxBDRead)
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if(RxEn & RxEn_q & RxBDRead)
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RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
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RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
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else
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else
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if(ShiftEnded | RxAbort) // igor !!! tx del ima tu ResetTxBDReady
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if(ShiftEnded | RxAbort)
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RxBDReady <=#Tp 1'b0;
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RxBDReady <=#Tp 1'b0;
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end
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end
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// Latching Rx buffer descriptor status
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// Latching Rx buffer descriptor status
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// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
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// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
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| Line 1735... |
Line 1738... |
RxOverrun <=#Tp 1'b1;
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RxOverrun <=#Tp 1'b1;
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end
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end
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// TX
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// TX
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// bit 15 od tx je ready
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// bit 15 ready
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// bit 14 od tx je interrupt (Tx buffer ali tx error bit se postavi v interrupt registru, ko se ta buffer odda)
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// bit 14 interrupt
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// bit 13 od tx je wrap
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// bit 13 wrap
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// bit 12 od tx je pad
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// bit 12 pad
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// bit 11 od tx je crc
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// bit 11 crc
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// bit 10 od tx je last (crc se doda le ce je bit 11 in hkrati bit 10)
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// bit 10 last
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// bit 9 od tx je pause request (control frame)
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// bit 9 pause request (control frame)
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// Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
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// bit 8 TxUnderRun
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// bit 8 od tx je defer indication done
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// bit 7-4 RetryCntLatched
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// bit 7 od tx je late collision done
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// bit 3 retransmittion limit
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// bit 6 od tx je retransmittion limit done
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// bit 2 LateCollLatched
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// bit 5 od tx je underrun done
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// bit 1 DeferLatched
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// bit 4 od tx je carrier sense lost
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// bit 0 CarrierSenseLost
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// bit [3:0] od tx je retry count done
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// RX
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// RX
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// bit 15 od rx je empty
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// bit 15 od rx je empty
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// bit 14 od rx je interrupt (Rx buffer ali rx frame received se postavi v interrupt registru, ko se ta buffer zapre)
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// bit 14 od rx je interrupt
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// bit 13 od rx je wrap
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// bit 13 od rx je wrap
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// bit 12 od rx je reserved
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// bit 12 od rx je reserved
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// bit 11 od rx je reserved
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// bit 11 od rx je reserved
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// bit 10 od rx je reserved
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// bit 10 od rx je reserved
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// bit 9 od rx je reserved
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// bit 9 od rx je reserved
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