| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.11 2002/02/15 17:07:39 mohor
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// Status was not written correctly when frames were discarted because of
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// address mismatch.
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//
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// Revision 1.10 2002/02/15 12:17:39 mohor
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// Revision 1.10 2002/02/15 12:17:39 mohor
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// RxStartFrm cleared when abort or retry comes.
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// RxStartFrm cleared when abort or retry comes.
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//
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//
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// Revision 1.9 2002/02/15 11:59:10 mohor
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// Revision 1.9 2002/02/15 11:59:10 mohor
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// Changes that were lost when updating from 1.5 to 1.8 fixed.
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// Changes that were lost when updating from 1.5 to 1.8 fixed.
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| Line 76... |
Line 80... |
//
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//
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//
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//
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//
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//
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//
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//
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// igor !!!
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// Build pause frame
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// Napravi, pause frame
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// Check GotData and evaluate data (abort or something like that comes before StartFrm)
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// m_wb_err_i should start status underrun or uverrun
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// Poskusi spremeniti vse signale na wb strani da bodo imeli enake koncnice (npr _wb),
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// r_RecSmall not used
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// vsi na MTxClk strani pa _txclk
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// Evaluiraj dato da pre start framom ni prisel abort ali kaj podobnega (kot je bilo v GotData, ki ga zbrisi)
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// Naj m_wb_err_i vzge status underrun ali uverrun
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`include "eth_defines.v"
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`include "eth_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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| Line 96... |
Line 96... |
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// WISHBONE common
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// WISHBONE common
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WB_CLK_I, WB_DAT_I, WB_DAT_O,
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WB_CLK_I, WB_DAT_I, WB_DAT_O,
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// WISHBONE slave
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// WISHBONE slave
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WB_ADR_I, WB_SEL_I, WB_WE_I, WB_ACK_O,
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WB_ADR_I, WB_WE_I, WB_ACK_O,
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BDCs,
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BDCs,
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Reset,
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Reset,
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// WISHBONE master
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// WISHBONE master
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| Line 115... |
Line 115... |
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//RX
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//RX
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MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
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MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
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// Register
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// Register
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r_TxEn, r_RxEn, r_TxBDNum, r_DmaEn, TX_BD_NUM_Wr, r_RecSmall,
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r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RecSmall,
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WillSendControlFrame, TxCtrlEndFrm, // igor !!! WillSendControlFrame gre najbrz ven
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WillSendControlFrame, TxCtrlEndFrm, // igor !!! WillSendControlFrame gre najbrz ven
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// Interrupts
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// Interrupts
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, TxC_IRQ, RxC_IRQ,
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// Rx Status
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// Rx Status
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InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
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InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
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ReceivedPacketTooBig, RxLength, LoadRxStatus,
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ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
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// Tx Status
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// Tx Status
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RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
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RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
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);
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);
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| Line 141... |
Line 141... |
input [31:0] WB_DAT_I; // WISHBONE data input
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input [31:0] WB_DAT_I; // WISHBONE data input
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output [31:0] WB_DAT_O; // WISHBONE data output
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output [31:0] WB_DAT_O; // WISHBONE data output
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// WISHBONE slave
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// WISHBONE slave
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input [9:2] WB_ADR_I; // WISHBONE address input
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input [9:2] WB_ADR_I; // WISHBONE address input
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input [3:0] WB_SEL_I; // WISHBONE byte select input
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input WB_WE_I; // WISHBONE write enable input
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input WB_WE_I; // WISHBONE write enable input
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input BDCs; // Buffer descriptors are selected
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input BDCs; // Buffer descriptors are selected
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output WB_ACK_O; // WISHBONE acknowledge output
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output WB_ACK_O; // WISHBONE acknowledge output
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// WISHBONE master
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// WISHBONE master
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| Line 168... |
Line 167... |
input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
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input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
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input DribbleNibble; // Extra nibble received
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input DribbleNibble; // Extra nibble received
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input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
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input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
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input [15:0] RxLength; // Length of the incoming frame
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input [15:0] RxLength; // Length of the incoming frame
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input LoadRxStatus; // Rx status was loaded
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input LoadRxStatus; // Rx status was loaded
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input ReceivedPacketGood;// Received packet's length and CRC are good
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// Tx Status signals
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// Tx Status signals
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input [3:0] RetryCntLatched; // Latched Retry Counter
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input [3:0] RetryCntLatched; // Latched Retry Counter
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input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
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input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
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input LateCollLatched; // Late collision occured
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input LateCollLatched; // Late collision occured
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| Line 205... |
Line 205... |
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//Register
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//Register
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input r_TxEn; // Transmit enable
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input r_TxEn; // Transmit enable
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input r_RxEn; // Receive enable
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input r_RxEn; // Receive enable
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input [7:0] r_TxBDNum; // Receive buffer descriptor number
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input [7:0] r_TxBDNum; // Receive buffer descriptor number
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input r_DmaEn; // DMA enable
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input TX_BD_NUM_Wr; // RxBDNumber written
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input TX_BD_NUM_Wr; // RxBDNumber written
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input r_RecSmall; // Receive small frames igor !!! tega uporabi
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input r_RecSmall; // Receive small frames igor !!! tega uporabi
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// Interrupts
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// Interrupts
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output TxB_IRQ;
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output TxB_IRQ;
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output TxE_IRQ;
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output TxE_IRQ;
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output RxB_IRQ;
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output RxB_IRQ;
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output RxF_IRQ;
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output RxE_IRQ;
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output Busy_IRQ;
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output Busy_IRQ;
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output TxC_IRQ;
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output RxC_IRQ;
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reg TxB_IRQ;
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reg TxE_IRQ;
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reg RxB_IRQ;
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reg RxE_IRQ;
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reg TxStartFrm;
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reg TxStartFrm;
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reg TxEndFrm;
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reg TxEndFrm;
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reg [7:0] TxData;
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reg [7:0] TxData;
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| Line 302... |
Line 310... |
wire StartTxBDRead;
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wire StartTxBDRead;
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wire TxIRQEn;
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wire TxIRQEn;
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wire WrapTxStatusBit;
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wire WrapTxStatusBit;
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wire RxIRQEn;
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wire WrapRxStatusBit;
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wire WrapRxStatusBit;
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wire [1:0] TxValidBytes;
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wire [1:0] TxValidBytes;
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wire [7:0] TempTxBDAddress;
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wire [7:0] TempTxBDAddress;
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| Line 405... |
Line 414... |
WbEn <=#Tp 1'b1;
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WbEn <=#Tp 1'b1;
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RxEn <=#Tp 1'b0;
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RxEn <=#Tp 1'b0;
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TxEn <=#Tp 1'b0;
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TxEn <=#Tp 1'b0;
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ram_addr <=#Tp 8'h0;
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ram_addr <=#Tp 8'h0;
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ram_di <=#Tp 32'h0;
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ram_di <=#Tp 32'h0;
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BDRead <=#Tp 1'b0;
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BDWrite <=#Tp 1'b0;
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end
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end
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else
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else
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begin
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begin
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// Switching between three stages depends on enable signals
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// Switching between three stages depends on enable signals
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casex ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
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casex ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
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| Line 960... |
Line 971... |
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assign TxIRQEn = TxStatus[14];
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assign TxIRQEn = TxStatus[14];
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assign WrapTxStatusBit = TxStatus[13];
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assign WrapTxStatusBit = TxStatus[13];
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assign PerPacketPad = TxStatus[12];
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assign PerPacketPad = TxStatus[12];
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assign PerPacketCrcEn = TxStatus[11];
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assign PerPacketCrcEn = TxStatus[11];
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//assign TxPauseRq = TxStatus[9]; // already used Ta gre ven, ker bo stvar izvedena preko registrov
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assign RxIRQEn = RxStatus[14];
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assign WrapRxStatusBit = RxStatus[13];
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assign WrapRxStatusBit = RxStatus[13];
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// Temporary Tx and Rx buffer descriptor address
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// Temporary Tx and Rx buffer descriptor address
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assign TempTxBDAddress[7:0] = {8{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
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assign TempTxBDAddress[7:0] = {8{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
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| Line 989... |
Line 1000... |
always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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RxBDAddress <=#Tp 8'h0;
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RxBDAddress <=#Tp 8'h0;
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else
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else
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if(TX_BD_NUM_Wr) // When r_TxBDNum is updated, RxBDAddress is also igor !!! ta del bi se lahko popravil
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if(TX_BD_NUM_Wr) // When r_TxBDNum is updated, RxBDAddress is also
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RxBDAddress <=#Tp WB_DAT_I[7:0];
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RxBDAddress <=#Tp WB_DAT_I[7:0];
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else
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else
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if(RxStatusWrite)
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if(RxStatusWrite)
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RxBDAddress <=#Tp TempRxBDAddress;
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RxBDAddress <=#Tp TempRxBDAddress;
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end
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end
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| Line 1691... |
Line 1702... |
if(RxStartFrm)
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if(RxStartFrm)
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RxAbortLatched <=#Tp 1'b0;
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RxAbortLatched <=#Tp 1'b0;
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end
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end
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// Interrupts
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assign TxB_IRQ = 1'b0;
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assign TxE_IRQ = 1'b0;
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assign RxB_IRQ = 1'b0;
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assign RxF_IRQ = 1'b0;
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assign Busy_IRQ = 1'b0;
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reg LoadStatusBlocked;
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reg LoadStatusBlocked;
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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| Line 1754... |
Line 1753... |
if(RxBufferFull & WriteRxDataToFifo_wb)
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if(RxBufferFull & WriteRxDataToFifo_wb)
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RxOverrun <=#Tp 1'b1;
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RxOverrun <=#Tp 1'b1;
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end
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end
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wire TxError;
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assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
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wire RxError;
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assign RxError = |RxStatusInLatched[6:0];
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// Tx Done Interrupt
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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TxB_IRQ <=#Tp 1'b0;
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else
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if(TxStatusWrite & TxIRQEn)
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TxB_IRQ <=#Tp ~TxError;
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else
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TxB_IRQ <=#Tp 1'b0;
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end
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// Tx Error Interrupt
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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TxE_IRQ <=#Tp 1'b0;
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else
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if(TxStatusWrite & TxIRQEn)
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TxE_IRQ <=#Tp TxError;
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else
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TxE_IRQ <=#Tp 1'b0;
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end
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// Rx Done Interrupt
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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RxB_IRQ <=#Tp 1'b0;
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else
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if(RxStatusWrite & RxIRQEn)
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RxB_IRQ <=#Tp ReceivedPacketGood;
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else
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RxB_IRQ <=#Tp 1'b0;
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end
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// Rx Error Interrupt
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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RxE_IRQ <=#Tp 1'b0;
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else
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if(RxStatusWrite & RxIRQEn)
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RxE_IRQ <=#Tp RxError;
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else
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RxE_IRQ <=#Tp 1'b0;
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end
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assign RxC_IRQ = 1'b0;
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assign TxC_IRQ = 1'b0;
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assign Busy_IRQ = 1'b0;
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// TX
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// TX
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// bit 15 ready
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// bit 15 ready
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// bit 14 interrupt
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// bit 14 interrupt
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// bit 13 wrap
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// bit 13 wrap
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// bit 12 pad
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// bit 12 pad
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