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https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 82 and 86
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Rev 86 |
Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.14 2002/03/02 19:12:40 mohor
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// Byte ordering changed (Big Endian used). casex changed with case because
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// Xilinx Foundation had problems. Tested in HW. It WORKS.
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//
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// Revision 1.13 2002/02/26 16:59:55 mohor
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// Revision 1.13 2002/02/26 16:59:55 mohor
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// Small fixes for external/internal DMA missmatches.
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// Small fixes for external/internal DMA missmatches.
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//
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//
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// Revision 1.12 2002/02/26 16:22:07 mohor
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// Revision 1.12 2002/02/26 16:22:07 mohor
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// Interrupts changed
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// Interrupts changed
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Line 1127... |
Line 1131... |
begin
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begin
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if(Reset)
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if(Reset)
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TxData <=#Tp 8'h0;
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TxData <=#Tp 8'h0;
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else
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else
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if(TxStartFrm_sync2 & ~TxStartFrm)
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if(TxStartFrm_sync2 & ~TxStartFrm)
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TxData <=#Tp TxData_wb[7:0];
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// TxData <=#Tp TxData_wb[7:0];
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TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
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else
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else
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if(TxUsedData & Flop)
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if(TxUsedData & Flop)
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begin
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begin
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case(TxByteCnt)
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case(TxByteCnt)
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// 0 : TxData <=#Tp TxDataLatched[7:0];
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// 0 : TxData <=#Tp TxDataLatched[7:0];
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