| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.15 2002/03/08 06:56:46 mohor
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// Big Endian problem when sending frames fixed.
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//
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// Revision 1.14 2002/03/02 19:12:40 mohor
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// Revision 1.14 2002/03/02 19:12:40 mohor
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// Byte ordering changed (Big Endian used). casex changed with case because
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// Byte ordering changed (Big Endian used). casex changed with case because
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// Xilinx Foundation had problems. Tested in HW. It WORKS.
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// Xilinx Foundation had problems. Tested in HW. It WORKS.
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//
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//
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// Revision 1.13 2002/02/26 16:59:55 mohor
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// Revision 1.13 2002/02/26 16:59:55 mohor
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| Line 1441... |
Line 1444... |
always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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RxStatusWriteLatched <=#Tp 1'b0;
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RxStatusWriteLatched <=#Tp 1'b0;
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else
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else
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if(RxStatusWrite)
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if(RxStatusWrite & ~RxStatusWrite_rck)
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RxStatusWriteLatched <=#Tp 1'b1;
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RxStatusWriteLatched <=#Tp 1'b1;
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else
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else
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if(RxStatusWrite_rck)
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if(RxStatusWrite_rck)
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RxStatusWriteLatched <=#Tp 1'b0;
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RxStatusWriteLatched <=#Tp 1'b0;
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end
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end
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| Line 1454... |
Line 1457... |
always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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RxStatusWrite_rck <=#Tp 1'b0;
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RxStatusWrite_rck <=#Tp 1'b0;
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else
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else
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RxStatusWrite_rck <=#Tp RxStatusWriteLatched;
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if(RxStatusWriteLatched)
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RxStatusWrite_rck <=#Tp 1'b1;
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else
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RxStatusWrite_rck <=#Tp 1'b0;
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end
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end
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reg RxEnableWindow;
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reg RxEnableWindow;
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| Line 1745... |
Line 1751... |
LoadStatusBlocked <=#Tp 1'b0;
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LoadStatusBlocked <=#Tp 1'b0;
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else
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else
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if(LoadRxStatus & ~RxAbortLatched)
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if(LoadRxStatus & ~RxAbortLatched)
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LoadStatusBlocked <=#Tp 1'b1;
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LoadStatusBlocked <=#Tp 1'b1;
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else
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else
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if(RxStatusWrite_rck)
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if(RxStatusWrite_rck | RxStartFrm)
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LoadStatusBlocked <=#Tp 1'b0;
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LoadStatusBlocked <=#Tp 1'b0;
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end
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end
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// LatchedRxLength[15:0]
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// LatchedRxLength[15:0]
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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