| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.19 2002/03/19 12:51:50 mohor
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// Comments in Slovene language removed.
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//
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// Revision 1.18 2002/03/19 12:46:52 mohor
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// Revision 1.18 2002/03/19 12:46:52 mohor
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// casex changed with case, fifo reset changed.
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// casex changed with case, fifo reset changed.
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//
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//
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// Revision 1.17 2002/03/09 16:08:45 mohor
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// Revision 1.17 2002/03/09 16:08:45 mohor
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// rx_fifo was not always cleared ok. Fixed.
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// rx_fifo was not always cleared ok. Fixed.
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| Line 650... |
Line 653... |
reg MasterWbRX;
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reg MasterWbRX;
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reg [31:0] m_wb_adr_o;
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reg [31:0] m_wb_adr_o;
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reg m_wb_cyc_o;
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reg m_wb_cyc_o;
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reg m_wb_stb_o;
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reg m_wb_stb_o;
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reg [3:0] m_wb_sel_o;
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reg m_wb_we_o;
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reg m_wb_we_o;
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wire TxLengthEq0;
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wire TxLengthEq0;
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wire TxLengthLt4;
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wire TxLengthLt4;
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wire WordAccFinished;
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wire HalfAccFinished;
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//Latching length from the buffer descriptor;
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//Latching length from the buffer descriptor;
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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| Line 669... |
Line 675... |
else
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else
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if(MasterWbTX & m_wb_ack_i)
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if(MasterWbTX & m_wb_ack_i)
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begin
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begin
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if(TxLengthLt4)
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if(TxLengthLt4)
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TxLength <=#Tp 16'h0;
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TxLength <=#Tp 16'h0;
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else
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else if(WordAccFinished)
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TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request
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TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request
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else if(HalfAccFinished)
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TxLength <=#Tp TxLength - 2'h2; // Length is subtracted at the data request
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else
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TxLength <=#Tp TxLength - 1'h1; // Length is subtracted at the data request
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end
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end
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end
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end
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assign WordAccFinished = &m_wb_sel_o[3:0];
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assign HalfAccFinished = &m_wb_sel_o[1:0];
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//Latching length from the buffer descriptor;
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//Latching length from the buffer descriptor;
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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LatchedTxLength <=#Tp 16'h0;
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LatchedTxLength <=#Tp 16'h0;
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| Line 691... |
Line 706... |
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reg BlockingIncrementTxPointer;
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reg BlockingIncrementTxPointer;
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reg [31:0] TxPointer;
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reg [31:0] TxPointer;
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reg [1:0] TxPointerLatched;
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reg [31:0] RxPointer;
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reg [31:0] RxPointer;
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reg [1:0] RxPointerLatched;
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wire TxBurstAcc;
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wire TxWordAcc;
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wire TxHalfAcc;
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wire TxByteAcc;
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wire RxBurstAcc;
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wire RxWordAcc;
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wire RxHalfAcc;
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wire RxByteAcc;
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//Latching Tx buffer pointer from buffer descriptor;
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//Latching Tx buffer pointer from buffer descriptor;
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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| Line 703... |
Line 731... |
else
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else
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if(TxEn & TxEn_q & TxPointerRead)
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if(TxEn & TxEn_q & TxPointerRead)
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TxPointer <=#Tp ram_do;
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TxPointer <=#Tp ram_do;
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else
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else
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if(MasterWbTX & ~BlockingIncrementTxPointer)
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if(MasterWbTX & ~BlockingIncrementTxPointer)
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TxPointer <=#Tp TxPointer + 4; // Pointer increment
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if(TxWordAcc)
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TxPointer <=#Tp TxPointer + 3'h4; // Word access
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else if(TxHalfAcc)
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TxPointer <=#Tp TxPointer + 2'h2; // Half access
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else
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TxPointer <=#Tp TxPointer + 1'h1; // Byte access
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end
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//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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TxPointerLatched[1:0] <=#Tp 0;
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else
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if(TxEn & TxEn_q & TxPointerRead)
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TxPointerLatched[1:0] <=#Tp ram_do[1:0];
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end
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end
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assign TxBurstAcc = ~TxPointer[3] & ~TxPointer[2] & ~TxPointer[1] & ~TxPointer[0]; // Add a counter that count burst to 4
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assign TxWordAcc = ~TxPointer[1] & ~TxPointer[0];
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assign TxHalfAcc = TxPointer[1] & ~TxPointer[0];
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assign TxByteAcc = TxPointer[0];
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wire [3:0] m_wb_sel_tmp_tx;
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reg [3:0] m_wb_sel_tmp_rx;
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assign m_wb_sel_tmp_tx[0] = TxWordAcc | TxHalfAcc | TxByteAcc & TxPointer[1];
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assign m_wb_sel_tmp_tx[1] = TxWordAcc | TxHalfAcc;
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assign m_wb_sel_tmp_tx[2] = TxWordAcc | | TxByteAcc & ~TxPointer[1];
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assign m_wb_sel_tmp_tx[3] = TxWordAcc;
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wire MasterAccessFinished;
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wire MasterAccessFinished;
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//Latching Tx buffer pointer from buffer descriptor;
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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BlockingIncrementTxPointer <=#Tp 0;
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BlockingIncrementTxPointer <=#Tp 0;
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else
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else
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| Line 767... |
Line 827... |
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assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
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assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
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assign m_wb_sel_o = 4'hf;
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//assign m_wb_sel_o = 4'hf;
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// Enabling master wishbone access to the memory for two devices TX and RX.
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// Enabling master wishbone access to the memory for two devices TX and RX.
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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| Line 780... |
Line 840... |
MasterWbRX <=#Tp 1'b0;
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MasterWbRX <=#Tp 1'b0;
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m_wb_adr_o <=#Tp 32'h0;
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m_wb_adr_o <=#Tp 32'h0;
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m_wb_cyc_o <=#Tp 1'b0;
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m_wb_cyc_o <=#Tp 1'b0;
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m_wb_stb_o <=#Tp 1'b0;
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m_wb_stb_o <=#Tp 1'b0;
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m_wb_we_o <=#Tp 1'b0;
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m_wb_we_o <=#Tp 1'b0;
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m_wb_sel_o <=#Tp 4'h0;
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end
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end
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else
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else
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begin
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begin
|
// Switching between two stages depends on enable signals
|
// Switching between two stages depends on enable signals
|
case ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished})
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case ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished})
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| Line 793... |
Line 854... |
MasterWbRX <=#Tp 1'b1;
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MasterWbRX <=#Tp 1'b1;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_cyc_o <=#Tp 1'b1;
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m_wb_cyc_o <=#Tp 1'b1;
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m_wb_stb_o <=#Tp 1'b1;
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m_wb_stb_o <=#Tp 1'b1;
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m_wb_we_o <=#Tp 1'b1;
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m_wb_we_o <=#Tp 1'b1;
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m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
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end
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end
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5'b00_10_0, 5'b00_10_1 :
|
5'b00_10_0, 5'b00_10_1 :
|
begin
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begin
|
MasterWbTX <=#Tp 1'b1; // idle and master read is needed (data read from tx buffer)
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MasterWbTX <=#Tp 1'b1; // idle and master read is needed (data read from tx buffer)
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MasterWbRX <=#Tp 1'b0;
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MasterWbRX <=#Tp 1'b0;
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m_wb_adr_o <=#Tp TxPointer;
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m_wb_adr_o <=#Tp TxPointer;
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m_wb_cyc_o <=#Tp 1'b1;
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m_wb_cyc_o <=#Tp 1'b1;
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m_wb_stb_o <=#Tp 1'b1;
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m_wb_stb_o <=#Tp 1'b1;
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m_wb_we_o <=#Tp 1'b0;
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m_wb_we_o <=#Tp 1'b0;
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m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
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end
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end
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5'b10_10_1 :
|
5'b10_10_1 :
|
begin
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begin
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MasterWbTX <=#Tp 1'b1; // master read and master read is needed (data read from tx buffer)
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MasterWbTX <=#Tp 1'b1; // master read and master read is needed (data read from tx buffer)
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MasterWbRX <=#Tp 1'b0;
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MasterWbRX <=#Tp 1'b0;
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m_wb_adr_o <=#Tp TxPointer;
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m_wb_adr_o <=#Tp TxPointer;
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m_wb_cyc_o <=#Tp 1'b1;
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m_wb_cyc_o <=#Tp 1'b1;
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m_wb_stb_o <=#Tp 1'b1;
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m_wb_stb_o <=#Tp 1'b1;
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m_wb_we_o <=#Tp 1'b0;
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m_wb_we_o <=#Tp 1'b0;
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m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
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end
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end
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5'b01_01_1 :
|
5'b01_01_1 :
|
begin
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begin
|
MasterWbTX <=#Tp 1'b0; // master write and master write is needed (data write to rx buffer)
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MasterWbTX <=#Tp 1'b0; // master write and master write is needed (data write to rx buffer)
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MasterWbRX <=#Tp 1'b1;
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MasterWbRX <=#Tp 1'b1;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_we_o <=#Tp 1'b1;
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m_wb_we_o <=#Tp 1'b1;
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m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
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end
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end
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5'b10_01_1, 5'b10_11_1 :
|
5'b10_01_1, 5'b10_11_1 :
|
begin
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begin
|
MasterWbTX <=#Tp 1'b0; // master read and master write is needed (data write to rx buffer)
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MasterWbTX <=#Tp 1'b0; // master read and master write is needed (data write to rx buffer)
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MasterWbRX <=#Tp 1'b1;
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MasterWbRX <=#Tp 1'b1;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_we_o <=#Tp 1'b1;
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m_wb_we_o <=#Tp 1'b1;
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m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
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end
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end
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5'b01_10_1, 5'b01_11_1 :
|
5'b01_10_1, 5'b01_11_1 :
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b1; // master write and master read is needed (data read from tx buffer)
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MasterWbTX <=#Tp 1'b1; // master write and master read is needed (data read from tx buffer)
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MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_adr_o <=#Tp TxPointer;
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m_wb_adr_o <=#Tp TxPointer;
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m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
|
m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
|
end
|
end
|
5'b10_00_1, 5'b01_00_1 :
|
5'b10_00_1, 5'b01_00_1 :
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b0; // whatever and no master read or write is needed (ack or err comes finishing previous access)
|
MasterWbTX <=#Tp 1'b0; // whatever and no master read or write is needed (ack or err comes finishing previous access)
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
| Line 846... |
Line 913... |
begin
|
begin
|
MasterWbTX <=#Tp MasterWbTX;
|
MasterWbTX <=#Tp MasterWbTX;
|
MasterWbRX <=#Tp MasterWbRX;
|
MasterWbRX <=#Tp MasterWbRX;
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m_wb_cyc_o <=#Tp m_wb_cyc_o;
|
m_wb_cyc_o <=#Tp m_wb_cyc_o;
|
m_wb_stb_o <=#Tp m_wb_stb_o;
|
m_wb_stb_o <=#Tp m_wb_stb_o;
|
|
m_wb_sel_o <=#Tp m_wb_sel_o;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
wire TxFifoClear;
|
wire TxFifoClear;
|
|
wire [31:0] tx_fifo_dat_i;
|
|
|
assign TxFifoClear = (TxAbort_wb | TxRetry_wb) & ~TxBDReady;
|
assign TxFifoClear = (TxAbort_wb | TxRetry_wb) & ~TxBDReady;
|
|
|
|
reg [23:16] LatchedData;
|
|
wire [23:16] TempData;
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
LatchedData[23:16] <=#Tp 0;
|
|
else
|
|
if(MasterWbTX & m_wb_ack_i & m_wb_sel_o[2])
|
|
LatchedData[23:16] <=#Tp m_wb_dat_i[23:16];
|
|
end
|
|
|
|
assign TempData[23:16] = m_wb_sel_o[2]? m_wb_dat_i[23:16] : LatchedData[23:16];
|
|
|
|
assign tx_fifo_dat_i[31:0] = {m_wb_dat_i[31:24], TempData[23:16], m_wb_dat_i[15:8], m_wb_dat_i[7:0]};
|
|
|
|
|
eth_fifo #(`TX_FIFO_DATA_WIDTH, `TX_FIFO_DEPTH, `TX_FIFO_CNT_WIDTH)
|
eth_fifo #(`TX_FIFO_DATA_WIDTH, `TX_FIFO_DEPTH, `TX_FIFO_CNT_WIDTH)
|
tx_fifo (.data_in(m_wb_dat_i), .data_out(TxData_wb), .clk(WB_CLK_I),
|
tx_fifo ( .data_in(tx_fifo_dat_i), .data_out(TxData_wb),
|
.reset(Reset), .write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb),
|
.clk(WB_CLK_I), .reset(Reset),
|
.clear(TxFifoClear), .full(TxBufferFull), .almost_full(TxBufferAlmostFull),
|
.write(MasterWbTX & m_wb_ack_i & m_wb_sel_o[0]), .read(ReadTxDataFromFifo_wb),
|
.almost_empty(TxBufferAlmostEmpty), .empty(TxBufferEmpty));
|
.clear(TxFifoClear), .full(TxBufferFull),
|
|
.almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty),
|
|
.empty(TxBufferEmpty)
|
|
);
|
|
|
|
|
reg StartOccured;
|
reg StartOccured;
|
reg TxStartFrm_sync1;
|
reg TxStartFrm_sync1;
|
reg TxStartFrm_sync2;
|
reg TxStartFrm_sync2;
|
| Line 1048... |
Line 1138... |
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
|
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
|
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
|
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
|
assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
|
assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
|
|
|
|
|
// assign ClearTxBDReady = ~TxUsedData & TxUsedData_q;
|
|
|
|
assign TPauseRq = 0;
|
assign TPauseRq = 0;
|
assign TxPauseTV[15:0] = TxLength[15:0];
|
assign TxPauseTV[15:0] = TxLength[15:0];
|
|
|
|
|
// Generating delayed signals
|
// Generating delayed signals
|
| Line 1138... |
Line 1226... |
|
|
// Tx data selection (latching)
|
// Tx data selection (latching)
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxData <=#Tp 8'h0;
|
TxData <=#Tp 0;
|
else
|
else
|
if(TxStartFrm_sync2 & ~TxStartFrm)
|
if(TxStartFrm_sync2 & ~TxStartFrm)
|
// TxData <=#Tp TxData_wb[7:0];
|
case(TxPointerLatched)
|
|
2'h0 : TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
|
|
2'h1 : TxData <=#Tp TxData_wb[23:16]; // Big Endian Byte Ordering
|
|
2'h2 : TxData <=#Tp TxData_wb[15:08]; // Big Endian Byte Ordering
|
|
2'h3 : TxData <=#Tp TxData_wb[07:00]; // Big Endian Byte Ordering
|
|
endcase
|
|
else
|
|
if(TxStartFrm & TxUsedData & TxPointerLatched==2'h3)
|
TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
|
TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
|
else
|
else
|
if(TxUsedData & Flop)
|
if(TxUsedData & Flop)
|
begin
|
begin
|
case(TxByteCnt)
|
case(TxByteCnt)
|
// 0 : TxData <=#Tp TxDataLatched[7:0];
|
|
// 1 : TxData <=#Tp TxDataLatched[15:8];
|
|
// 2 : TxData <=#Tp TxDataLatched[23:16];
|
|
// 3 : TxData <=#Tp TxDataLatched[31:24];
|
|
0 : TxData <=#Tp TxDataLatched[31:24]; // Big Endian Byte Ordering
|
0 : TxData <=#Tp TxDataLatched[31:24]; // Big Endian Byte Ordering
|
1 : TxData <=#Tp TxDataLatched[23:16];
|
1 : TxData <=#Tp TxDataLatched[23:16];
|
2 : TxData <=#Tp TxDataLatched[15:8];
|
2 : TxData <=#Tp TxDataLatched[15:8];
|
3 : TxData <=#Tp TxDataLatched[7:0];
|
3 : TxData <=#Tp TxDataLatched[7:0];
|
endcase
|
endcase
|
| Line 1166... |
Line 1257... |
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxDataLatched[31:0] <=#Tp 32'h0;
|
TxDataLatched[31:0] <=#Tp 32'h0;
|
else
|
else
|
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3)
|
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
|
TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
|
TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
|
end
|
end
|
|
|
|
|
// Tx under run
|
// Tx under run
|
| Line 1199... |
Line 1290... |
if(BlockingTxStatusWrite)
|
if(BlockingTxStatusWrite)
|
TxUnderRun <=#Tp 1'b0;
|
TxUnderRun <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
|
|
// Tx Byte counter
|
// Tx Byte counter
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxByteCnt <=#Tp 2'h0;
|
TxByteCnt <=#Tp 2'h0;
|
else
|
else
|
if(TxAbort_q | TxRetry_q)
|
if(TxAbort_q | TxRetry_q)
|
TxByteCnt <=#Tp 2'h0;
|
TxByteCnt <=#Tp 2'h0;
|
else
|
else
|
if(TxStartFrm & ~TxUsedData)
|
if(TxStartFrm & ~TxUsedData)
|
TxByteCnt <=#Tp 2'h1;
|
case(TxPointerLatched)
|
|
2'h0 : TxByteCnt <=#Tp 2'h1;
|
|
2'h1 : TxByteCnt <=#Tp 2'h2;
|
|
2'h2 : TxByteCnt <=#Tp 2'h3;
|
|
2'h3 : TxByteCnt <=#Tp 2'h0;
|
|
endcase
|
else
|
else
|
if(TxUsedData & Flop)
|
if(TxUsedData & Flop)
|
TxByteCnt <=#Tp TxByteCnt + 1;
|
TxByteCnt <=#Tp TxByteCnt + 1'b1;
|
end
|
end
|
|
|
|
|
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
reg ReadTxDataFromFifo_sync1;
|
reg ReadTxDataFromFifo_sync1;
|
| Line 1233... |
Line 1328... |
ReadTxDataFromFifo_tck <=#Tp 1'b0;
|
ReadTxDataFromFifo_tck <=#Tp 1'b0;
|
else
|
else
|
if(ReadTxDataFromFifo_syncb2)
|
if(ReadTxDataFromFifo_syncb2)
|
ReadTxDataFromFifo_tck <=#Tp 1'b0;
|
ReadTxDataFromFifo_tck <=#Tp 1'b0;
|
else
|
else
|
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord)
|
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
|
ReadTxDataFromFifo_tck <=#Tp 1'b1;
|
ReadTxDataFromFifo_tck <=#Tp 1'b1;
|
end
|
end
|
|
|
// Synchronizing TxStartFrm_wb to MTxClk
|
// Synchronizing TxStartFrm_wb to MTxClk
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
| Line 1407... |
Line 1502... |
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxPointer <=#Tp 32'h0;
|
RxPointer <=#Tp 32'h0;
|
else
|
else
|
if(RxEn & RxEn_q & RxPointerRead)
|
if(RxEn & RxEn_q & RxPointerRead)
|
RxPointer <=#Tp ram_do;
|
RxPointer <=#Tp {ram_do[31:2], 2'h0};
|
else
|
else
|
if(MasterWbRX & ~BlockingIncrementRxPointer)
|
if(MasterWbRX & ~BlockingIncrementRxPointer)
|
RxPointer <=#Tp RxPointer + 4; // Pointer increment
|
RxPointer <=#Tp RxPointer + 3'h4; // Word access (always word access. m_wb_sel_o are used for selecting bytes)
|
|
end
|
|
|
|
|
|
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RxPointerLatched[1:0] <=#Tp 0;
|
|
else
|
|
if(MasterWbRX & m_wb_ack_i) // After first write all m_wb_sel_tmp_rx are active
|
|
RxPointerLatched[1:0] <=#Tp 0;
|
|
else
|
|
if(RxEn & RxEn_q & RxPointerRead)
|
|
RxPointerLatched[1:0] <=#Tp ram_do[1:0];
|
|
end
|
|
|
|
|
|
always @ (RxPointerLatched)
|
|
begin
|
|
case(RxPointerLatched[1:0])
|
|
2'h0 : m_wb_sel_tmp_rx[3:0] = 4'hf;
|
|
2'h1 : m_wb_sel_tmp_rx[3:0] = 4'h7;
|
|
2'h2 : m_wb_sel_tmp_rx[3:0] = 4'h3;
|
|
2'h3 : m_wb_sel_tmp_rx[3:0] = 4'h1;
|
|
endcase
|
end
|
end
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
| Line 1490... |
Line 1610... |
|
|
reg ShiftEnded_tck;
|
reg ShiftEnded_tck;
|
reg ShiftEndedSync1;
|
reg ShiftEndedSync1;
|
reg ShiftEndedSync2;
|
reg ShiftEndedSync2;
|
wire StartShiftWillEnd;
|
wire StartShiftWillEnd;
|
assign StartShiftWillEnd = LastByteIn & (&RxByteCnt) | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
|
//assign StartShiftWillEnd = LastByteIn & (&RxByteCnt) | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
|
|
assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
|
|
|
// Indicating that data reception will end
|
// Indicating that data reception will end
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 1515... |
Line 1636... |
if(Reset)
|
if(Reset)
|
RxByteCnt <=#Tp 2'h0;
|
RxByteCnt <=#Tp 2'h0;
|
else
|
else
|
if(ShiftEnded_tck | RxAbort)
|
if(ShiftEnded_tck | RxAbort)
|
RxByteCnt <=#Tp 2'h0;
|
RxByteCnt <=#Tp 2'h0;
|
|
if(RxValid & RxStartFrm & RxBDReady)
|
|
case(RxPointerLatched)
|
|
2'h0 : RxByteCnt <=#Tp 2'h1;
|
|
2'h1 : RxByteCnt <=#Tp 2'h2;
|
|
2'h2 : RxByteCnt <=#Tp 2'h3;
|
|
2'h3 : RxByteCnt <=#Tp 2'h0;
|
|
endcase
|
else
|
else
|
if(RxValid & (RxStartFrm | RxEnableWindow) & RxBDReady | LastByteIn)
|
if(RxValid & RxEnableWindow & RxBDReady | LastByteIn)
|
RxByteCnt <=#Tp RxByteCnt + 1'b1;
|
RxByteCnt <=#Tp RxByteCnt + 1'b1;
|
end
|
end
|
|
|
|
|
// Indicates how many bytes are valid within the last word
|
// Indicates how many bytes are valid within the last word
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxValidBytes <=#Tp 2'h1;
|
RxValidBytes <=#Tp 2'h1;
|
else
|
else
|
if(ShiftEnded_tck | RxAbort)
|
if(RxValid & RxStartFrm)
|
RxValidBytes <=#Tp 2'h1;
|
case(RxPointerLatched)
|
|
2'h0 : RxValidBytes <=#Tp 2'h1;
|
|
2'h1 : RxValidBytes <=#Tp 2'h2;
|
|
2'h2 : RxValidBytes <=#Tp 2'h3;
|
|
2'h3 : RxValidBytes <=#Tp 2'h0;
|
|
endcase
|
else
|
else
|
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
|
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
|
RxValidBytes <=#Tp RxValidBytes + 1;
|
RxValidBytes <=#Tp RxValidBytes + 1;
|
end
|
end
|
|
|
| Line 1540... |
Line 1673... |
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxDataLatched1 <=#Tp 24'h0;
|
RxDataLatched1 <=#Tp 24'h0;
|
else
|
else
|
if(RxValid & RxBDReady & ~LastByteIn & (RxStartFrm | RxEnableWindow))
|
if(RxValid & RxBDReady & ~LastByteIn)
|
|
if(RxStartFrm)
|
|
begin
|
|
case(RxPointerLatched) // synopsys parallel_case
|
|
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
|
|
2'h1: RxDataLatched1[23:16] <=#Tp RxData;
|
|
2'h2: RxDataLatched1[15:8] <=#Tp RxData;
|
|
2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
|
|
endcase
|
|
end
|
|
else if (RxEnableWindow)
|
begin
|
begin
|
case(RxByteCnt) // synopsys parallel_case
|
case(RxByteCnt) // synopsys parallel_case
|
// 2'h0: RxDataLatched1[7:0] <=#Tp RxData;
|
|
// 2'h1: RxDataLatched1[15:8] <=#Tp RxData;
|
|
// 2'h2: RxDataLatched1[23:16] <=#Tp RxData;
|
|
// 2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
|
|
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
|
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
|
2'h1: RxDataLatched1[23:16] <=#Tp RxData;
|
2'h1: RxDataLatched1[23:16] <=#Tp RxData;
|
2'h2: RxDataLatched1[15:8] <=#Tp RxData;
|
2'h2: RxDataLatched1[15:8] <=#Tp RxData;
|
2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
|
2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
|
endcase
|
endcase
|
| Line 1564... |
Line 1703... |
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxDataLatched2 <=#Tp 32'h0;
|
RxDataLatched2 <=#Tp 32'h0;
|
else
|
else
|
if(SetWriteRxDataToFifo & ~ShiftWillEnd)
|
if(SetWriteRxDataToFifo & ~ShiftWillEnd)
|
// RxDataLatched2 <=#Tp {RxData, RxDataLatched1[23:0]};
|
|
RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
else
|
else
|
if(SetWriteRxDataToFifo & ShiftWillEnd)
|
if(SetWriteRxDataToFifo & ShiftWillEnd)
|
case(RxValidBytes)
|
case(RxValidBytes)
|
// 0 : RxDataLatched2 <=#Tp {RxData, RxDataLatched1[23:0]};
|
// 0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
// 1 : RxDataLatched2 <=#Tp { 24'h0, RxDataLatched1[7:0]};
|
// 1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
|
// 2 : RxDataLatched2 <=#Tp { 16'h0, RxDataLatched1[15:0]};
|
// 2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
|
// 3 : RxDataLatched2 <=#Tp { 8'h0, RxDataLatched1[23:0]};
|
// 3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0};
|
0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
|
1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
|
2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
|
2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
|
3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0};
|
3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0};
|
endcase
|
endcase
|
| Line 1586... |
Line 1724... |
reg WriteRxDataToFifoSync1;
|
reg WriteRxDataToFifoSync1;
|
reg WriteRxDataToFifoSync2;
|
reg WriteRxDataToFifoSync2;
|
|
|
|
|
// Indicating start of the reception process
|
// Indicating start of the reception process
|
assign SetWriteRxDataToFifo = (RxValid & RxBDReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) | (ShiftWillEnd & LastByteIn & (&RxByteCnt));
|
//assign SetWriteRxDataToFifo = (RxValid & RxBDReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) | (ShiftWillEnd & LastByteIn & (&RxByteCnt));
|
|
assign SetWriteRxDataToFifo = (RxValid & RxBDReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) | (RxValid & RxBDReady & RxStartFrm & (&RxPointerLatched)) | (ShiftWillEnd & LastByteIn & (&RxByteCnt));
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
WriteRxDataToFifo <=#Tp 1'b0;
|
WriteRxDataToFifo <=#Tp 1'b0;
|
