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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 96 and 97

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Rev 96 Rev 97
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.20  2002/03/25 16:19:12  mohor
 
// Any address can be used for Tx and Rx BD pointers. Address does not need
 
// to be aligned.
 
//
// Revision 1.19  2002/03/19 12:51:50  mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
// Comments in Slovene language removed.
// Comments in Slovene language removed.
//
//
// Revision 1.18  2002/03/19 12:46:52  mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
// casex changed with case, fifo reset changed.
// casex changed with case, fifo reset changed.
Line 1636... Line 1640...
  if(Reset)
  if(Reset)
    RxByteCnt <=#Tp 2'h0;
    RxByteCnt <=#Tp 2'h0;
  else
  else
  if(ShiftEnded_tck | RxAbort)
  if(ShiftEnded_tck | RxAbort)
    RxByteCnt <=#Tp 2'h0;
    RxByteCnt <=#Tp 2'h0;
 
  else
  if(RxValid & RxStartFrm & RxBDReady)
  if(RxValid & RxStartFrm & RxBDReady)
    case(RxPointerLatched)
    case(RxPointerLatched)
      2'h0 : RxByteCnt <=#Tp 2'h1;
      2'h0 : RxByteCnt <=#Tp 2'h1;
      2'h1 : RxByteCnt <=#Tp 2'h2;
      2'h1 : RxByteCnt <=#Tp 2'h2;
      2'h2 : RxByteCnt <=#Tp 2'h3;
      2'h2 : RxByteCnt <=#Tp 2'h3;

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