| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.23 2002/03/25 13:33:53 mohor
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// md_padoen_o changed to md_padoe_o. Signal was always active high, just
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// name was incorrect.
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//
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// Revision 1.22 2002/02/26 16:59:54 mohor
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// Revision 1.22 2002/02/26 16:59:54 mohor
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// Small fixes for external/internal DMA missmatches.
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// Small fixes for external/internal DMA missmatches.
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//
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//
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// Revision 1.21 2002/02/26 16:21:00 mohor
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// Revision 1.21 2002/02/26 16:21:00 mohor
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// Interrupts changed in the top file
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// Interrupts changed in the top file
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| Line 324... |
Line 328... |
wire TxC_IRQ; // Interrupt Tx Control Frame
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wire TxC_IRQ; // Interrupt Tx Control Frame
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wire RxC_IRQ; // Interrupt Rx Control Frame
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wire RxC_IRQ; // Interrupt Rx Control Frame
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wire DWord;
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wire DWord;
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wire BDAck;
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wire BDAck;
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wire [31:0] DMA_WB_DAT_O; // wb_dat_o that comes from the WishboneDMA module
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wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
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wire BDCs; // Buffer descriptor CS
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wire BDCs; // Buffer descriptor CS
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wire temp_wb_ack_o;
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wire [31:0] temp_wb_dat_o;
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wire temp_wb_err_o;
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`ifdef ETH_REGISTERED_OUTPUTS
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reg temp_wb_ack_o_reg;
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reg [31:0] temp_wb_dat_o_reg;
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reg temp_wb_err_o_reg;
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`endif
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assign DWord = &wb_sel_i;
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assign DWord = &wb_sel_i;
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assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10];
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assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10]; // 0x0 - 0x3FF
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assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10];
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assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10]; // 0x400 - 0x5FF
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assign wb_ack_o = RegCs | BDAck;
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assign temp_wb_ack_o = RegCs | BDAck;
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assign wb_err_o = wb_stb_i & wb_cyc_i & ~DWord;
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assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
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assign temp_wb_err_o = wb_stb_i & wb_cyc_i & ~DWord;
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`ifdef ETH_REGISTERED_OUTPUTS
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assign wb_ack_o = temp_wb_ack_o_reg;
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assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
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assign wb_err_o = temp_wb_err_o_reg;
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`else
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assign wb_ack_o = temp_wb_ack_o;
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assign wb_dat_o[31:0] = temp_wb_dat_o;
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assign wb_err_o = temp_wb_err_o;
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`endif
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// Selecting the WISHBONE output data
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assign wb_dat_o[31:0] = (RegCs & ~wb_we_i)? RegDataOut : DMA_WB_DAT_O;
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`ifdef ETH_REGISTERED_OUTPUTS
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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begin
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if(wb_rst_i)
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begin
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temp_wb_ack_o_reg <=#Tp 1'b0;
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temp_wb_dat_o_reg <=#Tp 32'h0;
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temp_wb_err_o_reg <=#Tp 1'b0;
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end
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else
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begin
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temp_wb_ack_o_reg <=#Tp temp_wb_ack_o;
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temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
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temp_wb_err_o_reg <=#Tp temp_wb_err_o;
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end
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end
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`endif
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// Connecting Ethernet registers
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// Connecting Ethernet registers
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eth_registers ethreg1
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eth_registers ethreg1
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(
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(
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| Line 590... |
Line 631... |
`else
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`else
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eth_wishbone wishbone
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eth_wishbone wishbone
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`endif
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`endif
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(
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(
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.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
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.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
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.WB_DAT_O(DMA_WB_DAT_O),
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.WB_DAT_O(BD_WB_DAT_O),
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// WISHBONE slave
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// WISHBONE slave
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.WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
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.WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
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.BDCs(BDCs), .WB_ACK_O(BDAck),
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.BDCs(BDCs), .WB_ACK_O(BDAck),
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| Line 629... |
Line 670... |
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
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.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
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.Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
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.Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
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.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ), .TxC_IRQ(TxC_IRQ),
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.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ), .TxC_IRQ(TxC_IRQ),
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.RxC_IRQ(RxC_IRQ),
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.RxC_IRQ(RxC_IRQ),
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.RxAbort(RxAbort),
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.RxAbort(RxAbort | (ShortFrame & ~r_RecSmall)),
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.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
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.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
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.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
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.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
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.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
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.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
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.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
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.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
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