| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.24 2002/04/22 14:15:42 mohor
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// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
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// selected in eth_defines.v
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//
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// Revision 1.23 2002/03/25 13:33:53 mohor
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// Revision 1.23 2002/03/25 13:33:53 mohor
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// md_padoen_o changed to md_padoe_o. Signal was always active high, just
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// md_padoen_o changed to md_padoe_o. Signal was always active high, just
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// name was incorrect.
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// name was incorrect.
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//
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//
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// Revision 1.22 2002/02/26 16:59:54 mohor
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// Revision 1.22 2002/02/26 16:59:54 mohor
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| Line 371... |
Line 375... |
temp_wb_dat_o_reg <=#Tp 32'h0;
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temp_wb_dat_o_reg <=#Tp 32'h0;
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temp_wb_err_o_reg <=#Tp 1'b0;
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temp_wb_err_o_reg <=#Tp 1'b0;
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end
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end
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else
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else
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begin
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begin
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temp_wb_ack_o_reg <=#Tp temp_wb_ack_o;
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temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg;
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temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
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temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
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temp_wb_err_o_reg <=#Tp temp_wb_err_o;
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temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
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end
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end
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end
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end
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`endif
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`endif
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| Line 637... |
Line 641... |
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// WISHBONE slave
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// WISHBONE slave
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.WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
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.WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
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.BDCs(BDCs), .WB_ACK_O(BDAck),
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.BDCs(BDCs), .WB_ACK_O(BDAck),
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.Reset(wb_rst_i),
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.Reset(r_Rst),
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`ifdef EXTERNAL_DMA
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`ifdef EXTERNAL_DMA
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.WB_REQ_O(wb_req_o), .WB_ND_O(wb_nd_o), .WB_RD_O(wb_rd_o),
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.WB_REQ_O(wb_req_o), .WB_ND_O(wb_nd_o), .WB_RD_O(wb_rd_o),
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.WB_ACK_I(wb_ack_i), .r_DmaEn(1'b1),
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.WB_ACK_I(wb_ack_i), .r_DmaEn(1'b1),
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`else
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`else
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