| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.25 2002/05/03 10:15:50 mohor
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// Outputs registered. Reset changed for eth_wishbone module.
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//
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// Revision 1.24 2002/04/22 14:15:42 mohor
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// Revision 1.24 2002/04/22 14:15:42 mohor
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// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
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// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
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// selected in eth_defines.v
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// selected in eth_defines.v
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//
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//
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// Revision 1.23 2002/03/25 13:33:53 mohor
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// Revision 1.23 2002/03/25 13:33:53 mohor
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| Line 151... |
Line 154... |
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
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wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
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// WISHBONE slave
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// WISHBONE slave
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wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
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wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
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`ifdef EXTERNAL_DMA
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wb_ack_i, wb_req_o, wb_nd_o, wb_rd_o,
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`else
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// WISHBONE master
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// WISHBONE master
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m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
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m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
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`endif
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//TX
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//TX
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mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
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mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
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//RX
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//RX
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| Line 193... |
Line 192... |
input wb_we_i; // WISHBONE write enable input
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input wb_we_i; // WISHBONE write enable input
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input wb_cyc_i; // WISHBONE cycle input
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input wb_cyc_i; // WISHBONE cycle input
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input wb_stb_i; // WISHBONE strobe input
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input wb_stb_i; // WISHBONE strobe input
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output wb_ack_o; // WISHBONE acknowledge output
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output wb_ack_o; // WISHBONE acknowledge output
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`ifdef EXTERNAL_DMA
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// DMA
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input [1:0] wb_ack_i; // DMA acknowledge input
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output [1:0] wb_req_o; // DMA request output
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output [1:0] wb_nd_o; // DMA force new descriptor output
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output wb_rd_o; // DMA restart descriptor output
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`else
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// WISHBONE master
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// WISHBONE master
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output [31:0] m_wb_adr_o;
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output [31:0] m_wb_adr_o;
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output [3:0] m_wb_sel_o;
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output [3:0] m_wb_sel_o;
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output m_wb_we_o;
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output m_wb_we_o;
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input [31:0] m_wb_dat_i;
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input [31:0] m_wb_dat_i;
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output [31:0] m_wb_dat_o;
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output [31:0] m_wb_dat_o;
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output m_wb_cyc_o;
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output m_wb_cyc_o;
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output m_wb_stb_o;
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output m_wb_stb_o;
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input m_wb_ack_i;
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input m_wb_ack_i;
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input m_wb_err_i;
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input m_wb_err_i;
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`endif
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// Tx
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// Tx
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input mtx_clk_pad_i; // Transmit clock (from PHY)
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input mtx_clk_pad_i; // Transmit clock (from PHY)
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output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
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output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
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| Line 347... |
Line 338... |
reg temp_wb_err_o_reg;
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reg temp_wb_err_o_reg;
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`endif
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`endif
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assign DWord = &wb_sel_i;
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assign DWord = &wb_sel_i;
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assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10]; // 0x0 - 0x3FF
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assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10]; // 0x0 - 0x3FF
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assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10]; // 0x400 - 0x5FF
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assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10]; // 0x400 - 0x7FF
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assign temp_wb_ack_o = RegCs | BDAck;
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assign temp_wb_ack_o = RegCs | BDAck;
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assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
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assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
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assign temp_wb_err_o = wb_stb_i & wb_cyc_i & ~DWord;
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assign temp_wb_err_o = wb_stb_i & wb_cyc_i & ~DWord;
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`ifdef ETH_REGISTERED_OUTPUTS
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`ifdef ETH_REGISTERED_OUTPUTS
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| Line 627... |
Line 618... |
end
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end
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// Connecting WishboneDMA module
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// Connecting Wishbone module
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`ifdef EXTERNAL_DMA
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eth_wishbonedma wishbone
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`else
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eth_wishbone wishbone
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eth_wishbone wishbone
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`endif
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(
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(
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.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
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.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
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.WB_DAT_O(BD_WB_DAT_O),
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.WB_DAT_O(BD_WB_DAT_O),
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// WISHBONE slave
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// WISHBONE slave
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.WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
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.WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
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.BDCs(BDCs), .WB_ACK_O(BDAck),
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.BDCs(BDCs), .WB_ACK_O(BDAck),
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.Reset(r_Rst),
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.Reset(r_Rst),
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`ifdef EXTERNAL_DMA
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.WB_REQ_O(wb_req_o), .WB_ND_O(wb_nd_o), .WB_RD_O(wb_rd_o),
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.WB_ACK_I(wb_ack_i), .r_DmaEn(1'b1),
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`else
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// WISHBONE master
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// WISHBONE master
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.m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
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.m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
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.m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
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.m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
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.m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
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.m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
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`endif
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//TX
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//TX
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.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
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.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
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.TxUsedData(TxUsedData), .TxData(TxData),
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.TxUsedData(TxUsedData), .TxData(TxData),
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.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
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.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
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