| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.28 2002/09/04 18:44:10 mohor
|
|
// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
|
|
// connected.
|
|
//
|
// Revision 1.27 2002/07/25 18:15:37 mohor
|
// Revision 1.27 2002/07/25 18:15:37 mohor
|
// RxAbort changed. Packets received with MRxErr (from PHY) are also
|
// RxAbort changed. Packets received with MRxErr (from PHY) are also
|
// aborted.
|
// aborted.
|
//
|
//
|
// Revision 1.26 2002/07/17 18:51:50 mohor
|
// Revision 1.26 2002/07/17 18:51:50 mohor
|
| Line 349... |
Line 353... |
assign DWord = &wb_sel_i;
|
assign DWord = &wb_sel_i;
|
assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10]; // 0x0 - 0x3FF
|
assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10]; // 0x0 - 0x3FF
|
assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10]; // 0x400 - 0x7FF
|
assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10]; // 0x400 - 0x7FF
|
assign temp_wb_ack_o = RegCs | BDAck;
|
assign temp_wb_ack_o = RegCs | BDAck;
|
assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
|
assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
|
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & ~DWord;
|
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | BDCs & r_Rst);
|
|
|
`ifdef ETH_REGISTERED_OUTPUTS
|
`ifdef ETH_REGISTERED_OUTPUTS
|
assign wb_ack_o = temp_wb_ack_o_reg;
|
assign wb_ack_o = temp_wb_ack_o_reg;
|
assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
|
assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
|
assign wb_err_o = temp_wb_err_o_reg;
|
assign wb_err_o = temp_wb_err_o_reg;
|
