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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac.v] - Diff between revs 21 and 22

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Rev 21 Rev 22
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.4  2001/10/18 12:07:11  mohor
 
// Status signals changed, Adress decoding changed, interrupt controller
 
// added.
 
//
// Revision 1.3  2001/09/24 15:02:56  mohor
// Revision 1.3  2001/09/24 15:02:56  mohor
// Defines changed (All precede with ETH_). Small changes because some
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
// demands).
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//
//
// 
// 
 
 
 
 
`include "eth_defines.v"
`include "eth_defines.v"
`include "eth_timescale.v"
`include "timescale.v"
 
 
 
 
module eth_top
module eth_top
(
(
  // WISHBONE common
  // WISHBONE common

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