Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.37 2002/11/13 22:25:36 tadejm
|
|
// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
|
|
//
|
// Revision 1.36 2002/10/18 17:04:20 tadejm
|
// Revision 1.36 2002/10/18 17:04:20 tadejm
|
// Changed BIST scan signals.
|
// Changed BIST scan signals.
|
//
|
//
|
// Revision 1.35 2002/10/11 13:36:58 mohor
|
// Revision 1.35 2002/10/11 13:36:58 mohor
|
// Typo error fixed. (When using Bist)
|
// Typo error fixed. (When using Bist)
|
Line 344... |
Line 347... |
|
|
|
|
wire RegCs; // Connected to registers
|
wire RegCs; // Connected to registers
|
wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
|
wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
|
wire r_RecSmall; // Receive small frames
|
wire r_RecSmall; // Receive small frames
|
wire r_Rst; // Reset
|
|
wire r_LoopBck; // Loopback
|
wire r_LoopBck; // Loopback
|
wire r_TxEn; // Tx Enable
|
wire r_TxEn; // Tx Enable
|
wire r_RxEn; // Rx Enable
|
wire r_RxEn; // Rx Enable
|
|
|
wire MRxDV_Lb; // Muxed MII receive data valid
|
wire MRxDV_Lb; // Muxed MII receive data valid
|
Line 409... |
Line 411... |
assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10]; // 0x0 - 0x3FF
|
assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10]; // 0x0 - 0x3FF
|
assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10]; // 0x400 - 0x7FF
|
assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10]; // 0x400 - 0x7FF
|
assign CsMiss = wb_stb_i & wb_cyc_i & DWord & wb_adr_i[11]; // 0x800 - 0xfFF
|
assign CsMiss = wb_stb_i & wb_cyc_i & DWord & wb_adr_i[11]; // 0x800 - 0xfFF
|
assign temp_wb_ack_o = RegCs | BDAck;
|
assign temp_wb_ack_o = RegCs | BDAck;
|
assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
|
assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
|
//assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | BDCs & r_Rst | CsMiss);
|
|
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | CsMiss);
|
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | CsMiss);
|
|
|
`ifdef ETH_REGISTERED_OUTPUTS
|
`ifdef ETH_REGISTERED_OUTPUTS
|
assign wb_ack_o = temp_wb_ack_o_reg;
|
assign wb_ack_o = temp_wb_ack_o_reg;
|
assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
|
assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
|
Line 450... |
Line 451... |
(
|
(
|
.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
|
.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
|
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
|
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
|
.DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
|
.DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
|
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
|
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
|
.r_DlyCrcEn(r_DlyCrcEn), .r_Rst(r_Rst), .r_FullD(r_FullD),
|
.r_DlyCrcEn(r_DlyCrcEn), .r_FullD(r_FullD),
|
.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
|
.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
|
.r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
|
.r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
|
.r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
|
.r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
|
.r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
|
.r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
|
.RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
|
.RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
|