| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2001/10/19 11:24:29 mohor
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// Number of addresses (wb_adr_i) minimized.
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//
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// Revision 1.5 2001/10/19 08:43:51 mohor
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// Revision 1.5 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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// simulation of the few cores in a one joined project.
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//
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//
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// Revision 1.4 2001/10/18 12:07:11 mohor
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// Revision 1.4 2001/10/18 12:07:11 mohor
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| Line 216... |
Line 219... |
wire [15:0] r_MaxFL; // Maximum frame length
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wire [15:0] r_MaxFL; // Maximum frame length
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wire [15:0] r_MinFL; // Minimum frame length
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wire [15:0] r_MinFL; // Minimum frame length
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wire [47:0] r_MAC; // MAC address
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wire [47:0] r_MAC; // MAC address
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wire [7:0] r_RxBDAddress; // Receive buffer descriptor base address
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wire [7:0] r_RxBDNum; // Receive buffer descriptor number
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wire [6:0] r_IPGT; //
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wire [6:0] r_IPGT; //
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wire [6:0] r_IPGR1; //
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wire [6:0] r_IPGR1; //
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wire [6:0] r_IPGR2; //
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wire [6:0] r_IPGR2; //
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wire [5:0] r_CollValid; //
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wire [5:0] r_CollValid; //
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wire r_TPauseRq; // Transmit PAUSE request pulse
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wire r_TPauseRq; // Transmit PAUSE request pulse
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wire [3:0] r_MaxRet; //
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wire [3:0] r_MaxRet; //
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wire r_NoBckof; //
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wire r_NoBckof; //
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wire r_ExDfrEn; //
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wire r_ExDfrEn; //
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wire RX_BD_ADR_Wr; // Write enable that writes RX_BD_ADR to the registers.
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wire RX_BD_NUM_Wr; // Write enable that writes RX_BD_NUM to the registers.
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wire TPauseRq; // Sinhronized Tx PAUSE request
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wire TPauseRq; // Sinhronized Tx PAUSE request
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wire [15:0] TxPauseTV; // Tx PAUSE timer value
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wire [15:0] TxPauseTV; // Tx PAUSE timer value
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wire r_TxFlow; // Tx flow control enable
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wire r_TxFlow; // Tx flow control enable
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wire r_IFG; // Minimum interframe gap for incoming packets
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wire r_IFG; // Minimum interframe gap for incoming packets
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| Line 278... |
Line 281... |
.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
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.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
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.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
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.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
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.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
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.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
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.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
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.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
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.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
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.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
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.r_RxBDAddress(r_RxBDAddress), .RX_BD_ADR_Wr(RX_BD_ADR_Wr), .int_o(int_o)
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.r_RxBDNum(r_RxBDNum), .RX_BD_NUM_Wr(RX_BD_NUM_Wr), .int_o(int_o)
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);
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);
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wire [7:0] RxData;
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wire [7:0] RxData;
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| Line 503... |
Line 506... |
.TxDone(TxDone), .TPauseRq(TPauseRq), .TxPauseTV(TxPauseTV),
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.TxDone(TxDone), .TPauseRq(TPauseRq), .TxPauseTV(TxPauseTV),
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.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad), .WillSendControlFrame(WillSendControlFrame),
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.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad), .WillSendControlFrame(WillSendControlFrame),
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.TxCtrlEndFrm(TxCtrlEndFrm),
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.TxCtrlEndFrm(TxCtrlEndFrm),
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// Register
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// Register
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.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_RxBDAddress(r_RxBDAddress),
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.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_RxBDNum(r_RxBDNum),
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.r_DmaEn(r_DmaEn), .RX_BD_ADR_Wr(RX_BD_ADR_Wr),
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.r_DmaEn(r_DmaEn), .RX_BD_NUM_Wr(RX_BD_NUM_Wr),
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//RX
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//RX
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.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
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.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
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.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
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.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
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.Busy_IRQ(Busy_IRQ), .RxF_IRQ(RxF_IRQ), .RxB_IRQ(RxB_IRQ),
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.Busy_IRQ(Busy_IRQ), .RxF_IRQ(RxF_IRQ), .RxB_IRQ(RxB_IRQ),
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