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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [timescale.v] - Diff between revs 338 and 346

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  timescale.v                                                 ////
////  timescale.v                                                 ////
////                                                              ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////  http://www.opencores.org/project,ethmac                     ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  All additional information is avaliable in the Readme.txt   ////

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