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[/] [ethmac10g/] [trunk/] [bench/] [Receive_tb.v] - Diff between revs 55 and 56

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Rev 55 Rev 56
Line 1... Line 1...
/*-------------------------------------------------------------------------------
/*-------------------------------------------------------------------------------
-- $Revision: 1.1 $ $Date: 2006-06-11 11:53:36 $
-- $Revision: 1.2 $ $Date: 2006-06-11 12:14:55 $
-- Title      : Demo testbench
-- Title      : Demo testbench
-- Project    : 10 Gigabit Ethernet MAC
-- Project    : 10 Gigabit Ethernet MAC
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File       : Receive_tb.v
-- File       : Receive_tb.v
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
Line 225... Line 225...
        frame1.ctrl[15] = 4'b1111;
        frame1.ctrl[15] = 4'b1111;
        frame1.ctrl[16] = 4'b1111;
        frame1.ctrl[16] = 4'b1111;
        frame1.ctrl[17] = 4'b1111;
        frame1.ctrl[17] = 4'b1111;
        frame1.ctrl[18] = 4'b1111;
        frame1.ctrl[18] = 4'b1111;
        frame1.ctrl[19] = 4'b1111;
        frame1.ctrl[19] = 4'b1111;
        frame1.ctrl[20] = 4'b1111;
        frame1.ctrl[20] = 4'b0111;
        frame1.ctrl[21] = 4'b0011;
        frame1.ctrl[21] = 4'b0000;
        frame1.ctrl[22] = 4'b0000;
        frame1.ctrl[22] = 4'b0000;
        frame1.ctrl[23] = 4'b0000;
        frame1.ctrl[23] = 4'b0000;
        frame1.ctrl[24] = 4'b0000;
        frame1.ctrl[24] = 4'b0000;
        frame1.ctrl[25] = 4'b0000;
        frame1.ctrl[25] = 4'b0000;
        frame1.ctrl[26] = 4'b0000;
        frame1.ctrl[26] = 4'b0000;
Line 396... Line 396...
  wire [63:0] rx_data;
  wire [63:0] rx_data;
  wire [7:0] rx_data_valid;
  wire [7:0] rx_data_valid;
  wire rx_good_frame;
  wire rx_good_frame;
  wire rx_bad_frame;
  wire rx_bad_frame;
  wire rx_clk;
  wire rx_clk;
  wire [28:0] rx_statistics_vector;
  wire [17:0] rxStatRegPlus;
  wire rx_statistics_valid;
  wire [2:0] rxCfgofRS;
 
  wire [1:0] rxTxLinkFault;
  wire [64:0] configuration_vector;
  wire [64:0] configuration_vector;
  reg  xgmii_rx_clk;
  reg  xgmii_rx_clk;
  reg  [31:0] xgmii_rxd;
  reg  [31:0] xgmii_rxd;
  reg  [3:0]  xgmii_rxc;
  reg  [3:0]  xgmii_rxc;
 
 
   reg   rx_monitor_finished;
 
   wire  simulation_finished;
 
 
 
 
 
  /*---------------------------------------------------------------------------
  /*---------------------------------------------------------------------------
  -- wire up Device Under Test
  -- wire up Device Under Test
  ---------------------------------------------------------------------------*/
  ---------------------------------------------------------------------------*/
        rxReceiveEngine uut (
        rxReceiveEngine uut (
                .rxclk_in(xgmii_rx_clk),
                .rxclk_in(xgmii_rx_clk),
Line 574... Line 571...
        rx_stimulus_send_idle;
        rx_stimulus_send_idle;
        rx_stimulus_send_idle;
        rx_stimulus_send_idle;
        rx_stimulus_send_frame(frame1.tobits(0));
        rx_stimulus_send_frame(frame1.tobits(0));
        rx_stimulus_send_idle;
        rx_stimulus_send_idle;
        rx_stimulus_send_idle;
        rx_stimulus_send_idle;
        rx_stimulus_send_idle;
 
        rx_stimulus_send_frame(frame2.tobits(0));
        rx_stimulus_send_frame(frame2.tobits(0));
        rx_stimulus_send_idle;
        rx_stimulus_send_idle;
        rx_stimulus_send_idle;
        rx_stimulus_send_idle;
        rx_stimulus_send_frame(frame3.tobits(0));
        rx_stimulus_send_frame(frame3.tobits(0));
        while (1)
        while (1)

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