OpenCores
URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [counter.v] - Diff between revs 39 and 41

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 39 Rev 41
Line 1... Line 1...
`timescale 100ps / 10ps
`include "timescale.v"
////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// Company: 
////                                                                                                                                                                    ////
// Engineer:
//// MODULE NAME: counter                                                                                               ////
 
////                                                                                                                                                                    ////
 
//// DESCRIPTION: 8bit counter                                    ////
 
////                                                              ////
 
////                                                                                                                                                                    ////
 
//// This file is part of the 10 Gigabit Ethernet IP core project ////
 
////  http://www.opencores.org/projects/ethmac10g/                                              ////
 
////                                                                                                                                                                    ////
 
//// AUTHOR(S):                                                                                                                                 ////
 
//// Zheng Cao                                                               ////
 
////                                                                                                    ////
 
//////////////////////////////////////////////////////////////////////
 
////                                                                                                                                                                    ////
 
//// Copyright (c) 2005 AUTHORS.  All rights reserved.                     ////
 
////                                                                                                                                                                    ////
 
//// This source file may be used and distributed without         ////
 
//// restriction provided that this copyright statement is not    ////
 
//// removed from the file and that any derivative work contains  ////
 
//// the original copyright notice and the associated disclaimer. ////
 
////                                                              ////
 
//// This source file is free software; you can redistribute it   ////
 
//// and/or modify it under the terms of the GNU Lesser General   ////
 
//// Public License as published by the Free Software Foundation; ////
 
//// either version 2.1 of the License, or (at your option) any   ////
 
//// later version.                                               ////
 
////                                                              ////
 
//// This source is distributed in the hope that it will be       ////
 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
 
//// details.                                                     ////
 
////                                                              ////
 
//// You should have received a copy of the GNU Lesser General    ////
 
//// Public License along with this source; if not, download it   ////
 
//// from http://www.opencores.org/lgpl.shtml                                                   ////
 
////                                                                                                                                                                    ////
 
//////////////////////////////////////////////////////////////////////
//
//
// Create Date:    15:53:19 11/22/05
// CVS REVISION HISTORY:
// Design Name:    
 
// Module Name:    counter
 
// Project Name:   
 
// Target Device:  
 
// Tool versions:  
 
// Description:
 
//
//
// Dependencies:
// $Log: not supported by cvs2svn $
 
// Revision 1.1  2005/12/25 16:43:10  Zheng Cao
// 
// 
// Revision:
 
// Revision 0.01 - File Created
 
// Additional Comments:
 
// 
// 
////////////////////////////////////////////////////////////////////////////////
//
 
//////////////////////////////////////////////////////////////////////
module counter(clk, reset, load, en, value);
module counter(clk, reset, load, en, value);
    input clk;
    input clk;
    input reset;
    input reset;
    input load;
    input load;
    input en;
    input en;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.