| Line 83... |
Line 83... |
output rx_good_frame;
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output rx_good_frame;
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output rx_bad_frame;
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output rx_bad_frame;
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// output [31:0]fcTxPauseData;
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// output [31:0]fcTxPauseData;
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|
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parameter TP = 1;
|
parameter TP = 1;
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parameter IDLE = 0, READ = 1, WAIT_TMP = 2, WAIT = 3;
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parameter IDLE = 0, READ = 2, WAIT_TMP = 3, WAIT = 1;
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|
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//////////////////////////////////////////////
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//////////////////////////////////////////////
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// Pipe Line Stage
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// Pipe Line Stage
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//////////////////////////////////////////////
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//////////////////////////////////////////////
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reg [63:0] rxd64_d1,rxd64_d2,rxd64_d3,CRC_DATA;
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reg [63:0] rxd64_d1,rxd64_d2,rxd64_d3,CRC_DATA;
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| Line 278... |
Line 278... |
|
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//////////////////////////////////////
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//////////////////////////////////////
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// Get Length/Type Field
|
// Get Length/Type Field
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//////////////////////////////////////
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//////////////////////////////////////
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|
|
// reg[15:0] lt_data;
|
reg[15:0] lt_data;
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// always@(posedge rxclk or posedge reset)begin
|
always@(posedge rxclk or posedge reset)begin
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// if (reset)
|
if (reset)
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// lt_data <=#TP 0;
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lt_data <=#TP 0;
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// else if (start_lt)
|
else if (start_lt)
|
// lt_data <=#TP rxd64_d1[47:32];
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lt_data <=#TP rxd64_d1[47:32];
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// else
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else
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// lt_data <=#TP lt_data;
|
lt_data <=#TP lt_data;
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// end
|
end
|
|
|
//tagged frame indicator
|
//tagged frame indicator
|
always@(posedge rxclk or posedge reset) begin
|
always@(posedge rxclk or posedge reset) begin
|
if (reset)
|
if (reset)
|
tagged_frame <=#TP 1'b0;
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tagged_frame <=#TP 1'b0;
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| Line 351... |
Line 351... |
one_frame_end <= 1'b0;
|
one_frame_end <= 1'b0;
|
end
|
end
|
|
|
reg fifo_rd_en;
|
reg fifo_rd_en;
|
reg[1:0] fifo_state;
|
reg[1:0] fifo_state;
|
reg rx_good_frame;
|
wire rx_good_frame;
|
reg rx_bad_frame;
|
wire rx_bad_frame;
|
reg check_reset;
|
reg check_reset;
|
always@(posedge rxclk or posedge reset) begin
|
always@(posedge rxclk or posedge reset) begin
|
if(reset) begin
|
if(reset) begin
|
fifo_rd_en <= 1'b0;
|
fifo_rd_en <= 1'b0;
|
fifo_state <= IDLE;
|
fifo_state <= IDLE;
|
rx_good_frame <= 1'b0;
|
|
rx_bad_frame <= 1'b0;
|
|
check_reset <= 1'b0;
|
check_reset <= 1'b0;
|
end
|
end
|
else
|
else
|
case (fifo_state)
|
case (fifo_state)
|
IDLE: begin
|
IDLE: begin
|
rx_good_frame <= 1'b0;
|
|
rx_bad_frame <= 1'b0;
|
|
check_reset <= 1'b0;
|
check_reset <= 1'b0;
|
fifo_state <= IDLE;
|
fifo_state <= IDLE;
|
fifo_rd_en <= 1'b0;
|
fifo_rd_en <= 1'b0;
|
if(~rxfifo_empty) begin
|
if(~rxfifo_empty) begin
|
fifo_rd_en <= 1'b1;
|
fifo_rd_en <= 1'b1;
|
fifo_state <= READ;
|
fifo_state <= WAIT_TMP;
|
end
|
end
|
end
|
end
|
READ: begin
|
READ: begin
|
check_reset <= 1'b0;
|
check_reset <= 1'b0;
|
fifo_rd_en <= 1'b1;
|
fifo_rd_en <= 1'b1;
|
rx_good_frame <= 1'b0;
|
|
rx_bad_frame <= 1'b0;
|
|
fifo_state <= READ;
|
fifo_state <= READ;
|
if(rx_data_valid_tmp!=8'hff)
|
if(rx_data_valid_tmp!=8'hff) begin
|
fifo_state <= WAIT_TMP;
|
fifo_state <= WAIT;
|
|
fifo_rd_en <= 1'b0;
|
|
end
|
end
|
end
|
WAIT_TMP: begin
|
WAIT_TMP: begin
|
if(rx_data_valid_tmp!=8'hff)
|
if(rx_data_valid_tmp == 8'hff)
|
fifo_state <= WAIT;
|
fifo_state <=READ;
|
|
else
|
|
fifo_state <=WAIT_TMP;
|
end
|
end
|
WAIT: begin
|
WAIT: begin
|
rx_good_frame <= 1'b0;
|
|
rx_bad_frame <= 1'b0;
|
|
fifo_state <= WAIT;
|
fifo_state <= WAIT;
|
check_reset <= 1'b0;
|
check_reset <= 1'b0;
|
fifo_rd_en <= 1'b0;
|
fifo_rd_en <= 1'b0;
|
if(bad_frame_get | good_frame_get)begin
|
if(bad_frame_get | good_frame_get)begin
|
rx_good_frame <= good_frame_get;
|
|
rx_bad_frame <= bad_frame_get;
|
|
fifo_state <= IDLE;
|
fifo_state <= IDLE;
|
check_reset <= 1'b1;
|
check_reset <= 1'b1;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
|
assign rx_good_frame = good_frame_get & (fifo_state == WAIT);
|
|
assign rx_bad_frame = bad_frame_get & (fifo_state == WAIT);
|
|
|
assign fifo_wr_en = receiving_d2;
|
assign fifo_wr_en = receiving_d2;
|
|
|
rxdatafifo rxdatain(.clk(rxclk),
|
rxdatafifo rxdatain(.clk(rxclk),
|
.sinit(reset),
|
.sinit(reset),
|
.din(rxd64_d3),
|
.din(rxd64_d3),
|
| Line 423... |
Line 420... |
.wr_en(fifo_wr_en),
|
.wr_en(fifo_wr_en),
|
.rd_en(fifo_rd_en),
|
.rd_en(fifo_rd_en),
|
.dout(rx_data_valid_tmp),
|
.dout(rx_data_valid_tmp),
|
.full(),
|
.full(),
|
.empty());
|
.empty());
|
|
|
reg fifo_rd_en_d1;
|
|
always@(posedge rxclk) begin
|
|
fifo_rd_en_d1 <=#TP fifo_rd_en;
|
|
end
|
|
|
|
reg [63:0] rx_data;
|
reg [63:0] rx_data;
|
always@(posedge rxclk or posedge reset) begin
|
always@(posedge rxclk or posedge reset) begin
|
if (reset)
|
if (reset) begin
|
rx_data <= 0;
|
rx_data <=#TP 0;
|
else
|
end
|
|
else begin
|
rx_data <=#TP rx_data_tmp;
|
rx_data <=#TP rx_data_tmp;
|
end
|
end
|
|
end
|
|
|
reg [7:0] rx_data_valid;
|
reg [7:0] rx_data_valid;
|
always@(posedge rxclk or posedge reset) begin
|
always@(posedge rxclk or posedge reset) begin
|
if (reset)
|
if (reset) begin
|
rx_data_valid <=#TP 0;
|
rx_data_valid <=#TP 0;
|
else
|
end
|
|
else if(fifo_state[1])begin
|
rx_data_valid <=#TP rx_data_valid_tmp;
|
rx_data_valid <=#TP rx_data_valid_tmp;
|
end
|
end
|
|
end
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
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No newline at end of file
|
