URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [rxDataPath.v] - Diff between revs 52 and 57

Rev 52	Rev 57
Line 321...	Line 321...
`rxc_final <=#TP 0;`	`rxc_final <=#TP 0;`
`else if (get_terminator & this_cycle)`	`else if (get_terminator & this_cycle)`
`rxc_final <=#TP rxc_end_data;`	`rxc_final <=#TP rxc_end_data;`
`else if (get_terminator_d1 & ~this_cycle)`	`else if (get_terminator_d1 & ~this_cycle)`
`rxc_final <=#TP rxc_end_data;`	`rxc_final <=#TP rxc_end_data;`
	`else if (get_error_code)`
	`rxc_final <=#TP 0;`
`else if (receiving)`	`else if (receiving)`
rxc_final <=`ALLONES8;	rxc_final <=#TP `ALLONES8;
`else`	`else`
`rxc_final <=0;`	`rxc_final <=#TP 0;`
`end`	`end`

`assign rxc_fifo = inband_fcs? ~rxc8_d3:rxc_final;`	`assign rxc_fifo = inband_fcs? ~rxc8_d3:rxc_final;`

`////////////////////////////////////////////////////////////////`	`////////////////////////////////////////////////////////////////`
Line 432...	Line 434...
`end`	`end`
`end`	`end`

`reg [7:0] rx_data_valid;`	`reg [7:0] rx_data_valid;`
`always@(posedge rxclk or posedge reset) begin`	`always@(posedge rxclk or posedge reset) begin`
`if (reset) begin`	`if (reset)`
`rx_data_valid <=#TP 0;`	`rx_data_valid <=#TP 0;`
`end`	`else if(fifo_state[1])`
`else if(fifo_state[1])begin`
`rx_data_valid <=#TP rx_data_valid_tmp;`	`rx_data_valid <=#TP rx_data_valid_tmp;`
`end`	`else`
	`rx_data_valid <=#TP 0;`
`end`	`end`

`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`