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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [rxReceiveEngine.ucf] - Diff between revs 39 and 70

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Rev 39 Rev 70
Line 17... Line 17...
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Area Constraints
AREA_GROUP "AG_rxReceiveEngine" RANGE = SLICE_X2Y37:SLICE_X33Y2 ;
AREA_GROUP "AG_rxReceiveEngine" RANGE = SLICE_X2Y37:SLICE_X33Y2 ;
INST "/" AREA_GROUP = "AG_rxReceiveEngine" ;
INST "/" AREA_GROUP = "AG_rxReceiveEngine" ;
#PACE: Start of PACE Prohibit Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
#PACE: End of Constraints generated by PACE
NET "rxclk_in" TNM_NET = "rxclk_in";
NET "xgmii_rxclk" TNM_NET = "xgmii_rxclk";
TIMESPEC "TS_rxclk_in" = PERIOD "rxclk_in" 6.5 ns HIGH 50 %;
TIMESPEC "TS_xgmii_rxclk" = PERIOD "xgmii_rxclk" 6.5 ns HIGH 50 %;
#OFFSET = IN 2 ns BEFORE "rxclk_in" HIGH ;
#OFFSET = IN 2 ns BEFORE "xgmii_rxclk" HIGH ;
#OFFSET = IN 2 ns BEFORE "xgmii_rxclk" HIGH ;
#OFFSET = IN 2 ns BEFORE "xgmii_rxclk" HIGH ;

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