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`include "timescale.v"
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`include "timescale.v"
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`include "xgiga_define.v"
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`include "xgiga_define.v"
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module rxReceiveEngine(rxclk_in, reset_in, rxd_in, rxc_in, rxStatRegPlus,
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module rxReceiveEngine(rxclk_in, reset_in, rxd_in, rxc_in, rxStatRegPlus,
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cfgRxRegData_in, rx_data, rx_data_valid, rx_good_frame,
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cfgRxRegData_in, rx_data, rx_data_valid, rx_good_frame, rxclk_out,
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rx_bad_frame, rxCfgofRS, rxTxLinkFault);//, fcTxPauseData, fcTxPauseValid);
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rx_bad_frame, rxCfgofRS, rxTxLinkFault);//, fcTxPauseData, fcTxPauseValid);
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input rxclk_in; //Input clock of receive engine
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input rxclk_in; //Input clock of receive engine
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input reset_in; //Globle reset of receive engine
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input reset_in; //Globle reset of receive engine
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input [31:0] rxd_in; //XGMII RXD
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input [31:0] rxd_in; //XGMII RXD
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input [3:0] rxc_in; //XGMII RXC
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input [3:0] rxc_in; //XGMII RXC
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output [18:0] rxStatRegPlus; //Signals for statistics
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output [17:0] rxStatRegPlus; //Signals for statistics
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input [64:0] cfgRxRegData_in; //Signals for configuration
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input [64:0] cfgRxRegData_in; //Signals for configuration
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output [63:0] rx_data; //Received data sent to upper layer
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output [63:0] rx_data; //Received data sent to upper layer
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output [7:0] rx_data_valid; //Receive data valid indicator
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output [7:0] rx_data_valid; //Receive data valid indicator
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output rx_good_frame; //Indicate that a good frame has been received
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output rx_good_frame; //Indicate that a good frame has been received
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output rx_bad_frame; //Indicate that a bad frame has been received
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output rx_bad_frame; //Indicate that a bad frame has been received
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output[2:0] rxCfgofRS; //
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output[2:0] rxCfgofRS; //
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output [1:0] rxTxLinkFault;
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output [1:0] rxTxLinkFault;
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output rxclk_out;
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// output [31:0] fcTxPauseData;
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// output [31:0] fcTxPauseData;
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// output fcTxPauseValid;
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// output fcTxPauseValid;
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parameter TP =1;
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parameter TP =1;
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// assign fcTxPauseData = {16{1'b0},rxd64[15:0]};
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// assign fcTxPauseData = {16{1'b0},rxd64[15:0]};
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////////////////////////////////////////
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////////////////////////////////////////
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// Receive Clock Generator
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// Receive Clock Generator
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////////////////////////////////////////
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////////////////////////////////////////
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assign rxclk_out = rxclk;
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rxClkgen rxclk_gen(.rxclk_in(rxclk_in),
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rxClkgen rxclk_gen(.rxclk_in(rxclk_in),
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.reset(reset_dcm),
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.reset(reset_dcm),
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.rxclk(rxclk), // system clock
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.rxclk(rxclk), // system clock
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.rxclk_180(rxclk_180), //reversed clock
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.rxclk_180(rxclk_180), //reversed clock
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.locked(locked)
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.locked(locked)
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