OpenCores
URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [rxReceiveEngine.v] - Diff between revs 56 and 60

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 56 Rev 60
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS REVISION HISTORY:
// CVS REVISION HISTORY:
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.3  2006/06/11 12:15:11  fisher5090
 
// no message
 
//
// Revision 1.1  2005/12/25 16:43:10  Zheng Cao
// Revision 1.1  2005/12/25 16:43:10  Zheng Cao
// No flow control included
// No flow control included
// 
// 
//
//
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
`include "timescale.v"
`include "timescale.v"
`include "xgiga_define.v"
`include "xgiga_define.v"
 
 
module rxReceiveEngine(rxclk_in, reset_in, rxd_in, rxc_in, rxStatRegPlus,
module rxReceiveEngine(xgmii_rxclk, reset_in, xgmii_rxd, xgmii_rxc, rxStatRegPlus,
                       cfgRxRegData_in, rx_data, rx_data_valid, rx_good_frame, rxclk_out,
                       cfgRxRegData_in, rx_data, rx_data_valid, rx_good_frame, rxclk_out,
                       rx_bad_frame, rxCfgofRS, rxTxLinkFault);//, fcTxPauseData, fcTxPauseValid);
                       rx_bad_frame, rxCfgofRS, rxTxLinkFault);//, fcTxPauseData, fcTxPauseValid);
    input rxclk_in; //Input clock of receive engine
    input xgmii_rxclk; //Input clock of receive engine
    input reset_in; //Globle reset of receive engine
    input reset_in; //Globle reset of receive engine
    input [31:0] rxd_in; //XGMII RXD
    input [31:0] xgmii_rxd; //XGMII RXD
    input [3:0] rxc_in;  //XGMII RXC
    input [3:0] xgmii_rxc;  //XGMII RXC
    output [17:0] rxStatRegPlus; //Signals for statistics        
    output [17:0] rxStatRegPlus; //Signals for statistics        
    input [64:0] cfgRxRegData_in; //Signals for configuration
    input [64:0] cfgRxRegData_in; //Signals for configuration
    output [63:0] rx_data; //Received data sent to upper layer
    output [63:0] rx_data; //Received data sent to upper layer
    output [7:0] rx_data_valid; //Receive data valid indicator
    output [7:0] rx_data_valid; //Receive data valid indicator
    output rx_good_frame; //Indicate that a good frame has been received
    output rx_good_frame; //Indicate that a good frame has been received
Line 209... Line 212...
 
 
         ////////////////////////////////////////
         ////////////////////////////////////////
         // Receive Clock Generator
         // Receive Clock Generator
         //////////////////////////////////////// 
         //////////////////////////////////////// 
    assign rxclk_out = rxclk;
    assign rxclk_out = rxclk;
         rxClkgen rxclk_gen(.rxclk_in(rxclk_in),
         rxClkgen rxclk_gen(.rxclk_in(xgmii_rxclk),
                            .reset(reset_dcm),
                            .reset(reset_dcm),
                                                          .rxclk(rxclk),    // system clock
                                                          .rxclk(rxclk),    // system clock
                                                          .rxclk_180(rxclk_180), //reversed clock
                                                          .rxclk_180(rxclk_180), //reversed clock
                                                          .locked(locked)
                                                          .locked(locked)
                                                          );
                                                          );
Line 269... Line 272...
                         .crc_check_invalid(crc_check_invalid), .crc_check_valid(crc_check_valid),.receiving(receiving),.receiving_d1(receiving_d1),
                         .crc_check_invalid(crc_check_invalid), .crc_check_valid(crc_check_valid),.receiving(receiving),.receiving_d1(receiving_d1),
                                                  .get_terminator_d1(get_terminator_d1), .wait_crc_check(wait_crc_check),.get_error_code(get_error_code));
                                                  .get_terminator_d1(get_terminator_d1), .wait_crc_check(wait_crc_check),.get_error_code(get_error_code));
    /////////////////////////////////////
    /////////////////////////////////////
         // RS Layer
         // RS Layer
         /////////////////////////////////////
         /////////////////////////////////////
    rxRSLayer rx_rs(.rxclk(rxclk), .rxclk_180(rxclk_180), .reset(reset), .link_fault(link_fault), .rxd64(rxd64), .rxc8(rxc8), .rxd_in(rxd_in), .rxc_in(rxc_in));
    rxRSLayer rx_rs(.rxclk(rxclk), .rxclk_180(rxclk_180), .reset(reset), .link_fault(link_fault), .rxd64(rxd64), .rxc8(rxc8), .rxd_in(xgmii_rxd), .rxc_in(xgmii_rxc));
 
 
         /////////////////////////////////////
         /////////////////////////////////////
         // Statistic module
         // Statistic module
         /////////////////////////////////////
         /////////////////////////////////////
         rxStatModule rx_stat(.rxclk(rxclk),.reset(reset),.good_frame_get(good_frame_get), .large_error(large_error),.small_error(small_error), .crc_check_invalid(crc_check_invalid),
         rxStatModule rx_stat(.rxclk(rxclk),.reset(reset),.good_frame_get(good_frame_get), .large_error(large_error),.small_error(small_error), .crc_check_invalid(crc_check_invalid),

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.