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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [rxReceiveEngine.v] - Diff between revs 70 and 71

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Rev 70 Rev 71
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS REVISION HISTORY:
// CVS REVISION HISTORY:
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.6  2006/06/16 06:39:59  fisher5090
 
// no message
 
//
// Revision 1.5  2006/06/16 06:36:28  Zheng Cao
// Revision 1.5  2006/06/16 06:36:28  Zheng Cao
// no message
// no message
//
//
// Revision 1.4  2006/06/12 10:02:19  Zheng Cao
// Revision 1.4  2006/06/12 10:02:19  Zheng Cao
// change rxd_in, rxc_in and rxclk_in signals'name to xgmii_rxd, xgmii_rxc and xgmii_rxclk
// change rxd_in, rxc_in and rxclk_in signals'name to xgmii_rxd, xgmii_rxc and xgmii_rxclk
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
`include "timescale.v"
`include "timescale.v"
`include "xgiga_define.v"
`include "xgiga_define.v"
 
 
module rxReceiveEngine(xgmii_rxclk, reset_in, xgmii_rxd, xgmii_rxc, rxStatRegPlus,
module rxReceiveEngine(xgmii_rxclk, rxclk_2x, reset_in, xgmii_rxd, xgmii_rxc, rxStatRegPlus,
                       cfgRxRegData_in, rx_data, rx_data_valid, rx_good_frame, rxclk_out,
                       cfgRxRegData_in, rx_data, rx_data_valid, rx_good_frame, rxclk_out,
                       rx_bad_frame, rxCfgofRS, rxTxLinkFault);//, fcTxPauseData, fcTxPauseValid);
                       rx_bad_frame, rxCfgofRS, rxTxLinkFault);//, fcTxPauseData, fcTxPauseValid);
    input xgmii_rxclk; //Input clock of receive engine
    input xgmii_rxclk; //Input clock of receive engine
 
    input rxclk_2x;
    input reset_in; //Globle reset of receive engine
    input reset_in; //Globle reset of receive engine
    input [31:0] xgmii_rxd; //XGMII RXD
    input [31:0] xgmii_rxd; //XGMII RXD
    input [3:0] xgmii_rxc;  //XGMII RXC
    input [3:0] xgmii_rxc;  //XGMII RXC
    output [17:0] rxStatRegPlus; //Signals for statistics        
    output [17:0] rxStatRegPlus; //Signals for statistics        
    input [64:0] cfgRxRegData_in; //Signals for configuration
    input [64:0] cfgRxRegData_in; //Signals for configuration
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                   .crc_check_invalid(crc_check_invalid), .crc_check_valid(crc_check_valid),.receiving(receiving),.receiving_d1(receiving_d1),
                   .crc_check_invalid(crc_check_invalid), .crc_check_valid(crc_check_valid),.receiving(receiving),.receiving_d1(receiving_d1),
                   .get_terminator_d1(get_terminator_d1), .wait_crc_check(wait_crc_check),.get_error_code(get_error_code));
                   .get_terminator_d1(get_terminator_d1), .wait_crc_check(wait_crc_check),.get_error_code(get_error_code));
   /////////////////////////////////////
   /////////////////////////////////////
   // RS Layer
   // RS Layer
   /////////////////////////////////////
   /////////////////////////////////////
    rxRSLayer rx_rs(.rxclk(rxclk), .rxclk_180(rxclk_180), .reset(reset), .link_fault(link_fault), .rxd64(rxd64), .rxc8(rxc8), .rxd_in(xgmii_rxd), .rxc_in(xgmii_rxc));
    rxRSLayer rx_rs(.rxclk(rxclk), .rxclk_180(rxclk_180), .rxclk_2x(rxclk_2x), .reset(reset), .link_fault(link_fault), .rxd64(rxd64), .rxc8(rxc8), .rxd_in(xgmii_rxd), .rxc_in(xgmii_rxc));
 
 
   /////////////////////////////////////
   /////////////////////////////////////
   // Statistic module
   // Statistic module
   /////////////////////////////////////
   /////////////////////////////////////
   rxStatModule rx_stat(.rxclk(rxclk),.reset(reset),.good_frame_get(good_frame_get), .large_error(large_error),.small_error(small_error), .crc_check_invalid(crc_check_invalid),
   rxStatModule rx_stat(.rxclk(rxclk),.reset(reset),.good_frame_get(good_frame_get), .large_error(large_error),.small_error(small_error), .crc_check_invalid(crc_check_invalid),

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