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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.pkt_ack_pkg.all;
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use work.pkt_ack_pkg.all;
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use work.desc_mgr_pkg.all;
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use work.desc_mgr_pkg.all;
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library unisim;
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library unisim;
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use unisim.vcomponents.all;
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use unisim.vcomponents.all;
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library work;
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entity afck_10g_2 is
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entity afck_10g_2 is
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port (
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port (
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gtx10g_txn : out std_logic_vector(3 downto 0);
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gtx10g_txn : out std_logic_vector(3 downto 0);
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Line 101... |
signal clk_user : std_logic;
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signal clk_user : std_logic;
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component ten_gig_eth_pcs_pma_0 is
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component ten_gig_eth_pcs_pma_0 is
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port (
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port (
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dclk : in std_logic;
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dclk : in std_logic;
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rxrecclk_out : out std_logic;
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refclk_p : in std_logic;
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refclk_p : in std_logic;
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refclk_n : in std_logic;
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refclk_n : in std_logic;
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sim_speedup_control : in std_logic;
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sim_speedup_control : in std_logic;
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core_clk156_out : out std_logic;
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coreclk_out : out std_logic;
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qplloutclk_out : out std_logic;
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qplloutclk_out : out std_logic;
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qplloutrefclk_out : out std_logic;
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qplloutrefclk_out : out std_logic;
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qplllock_out : out std_logic;
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qplllock_out : out std_logic;
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txusrclk_out : out std_logic;
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txusrclk_out : out std_logic;
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txusrclk2_out : out std_logic;
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txusrclk2_out : out std_logic;
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areset_clk156_out : out std_logic;
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areset_datapathclk_out : out std_logic;
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gttxreset_out : out std_logic;
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gttxreset_out : out std_logic;
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gtrxreset_out : out std_logic;
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gtrxreset_out : out std_logic;
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txuserrdy_out : out std_logic;
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txuserrdy_out : out std_logic;
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reset_counter_done_out : out std_logic;
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reset_counter_done_out : out std_logic;
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reset : in std_logic;
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reset : in std_logic;
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Line 149... |
rxp : in std_logic;
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rxp : in std_logic;
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rxn : in std_logic;
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rxn : in std_logic;
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configuration_vector : in std_logic_vector (535 downto 0);
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configuration_vector : in std_logic_vector (535 downto 0);
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status_vector : out std_logic_vector (447 downto 0);
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status_vector : out std_logic_vector (447 downto 0);
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core_status : out std_logic_vector (7 downto 0);
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core_status : out std_logic_vector (7 downto 0);
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resetdone : out std_logic;
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resetdone_out : out std_logic;
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signal_detect : in std_logic;
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signal_detect : in std_logic;
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tx_fault : in std_logic;
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tx_fault : in std_logic;
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drp_req : out std_logic;
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drp_req : out std_logic;
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drp_gnt : in std_logic;
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drp_gnt : in std_logic;
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drp_den_o : out std_logic;
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drp_den_o : out std_logic;
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Line 173... |
end component ten_gig_eth_pcs_pma_0;
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end component ten_gig_eth_pcs_pma_0;
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component ten_gig_eth_pcs_pma_1 is
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component ten_gig_eth_pcs_pma_1 is
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port (
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port (
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dclk : in std_logic;
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dclk : in std_logic;
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clk156 : in std_logic;
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rxrecclk_out : out std_logic;
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coreclk : in std_logic;
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txusrclk : in std_logic;
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txusrclk : in std_logic;
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txusrclk2 : in std_logic;
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txusrclk2 : in std_logic;
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txclk322 : out std_logic;
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txoutclk : out std_logic;
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areset : in std_logic;
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areset : in std_logic;
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areset_clk156 : in std_logic;
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areset_coreclk : in std_logic;
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gttxreset : in std_logic;
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gttxreset : in std_logic;
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gtrxreset : in std_logic;
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gtrxreset : in std_logic;
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sim_speedup_control : in std_logic;
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sim_speedup_control : in std_logic;
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txuserrdy : in std_logic;
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txuserrdy : in std_logic;
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qplllock : in std_logic;
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qplllock : in std_logic;
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| Line 303... |
Line 306... |
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il1 : if n = 0 generate
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il1 : if n = 0 generate
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ten_gig_eth_pcs_pma_0_1 : ten_gig_eth_pcs_pma_0
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ten_gig_eth_pcs_pma_0_1 : ten_gig_eth_pcs_pma_0
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port map (
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port map (
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dclk => clk_user,
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dclk => clk_user,
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sim_speedup_control => '0',
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rxrecclk_out => open, --??
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refclk_p => refclk_p,
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refclk_p => refclk_p,
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refclk_n => refclk_n,
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refclk_n => refclk_n,
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reset => reset,
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sim_speedup_control => '0',
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resetdone => s_resetdone,
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coreclk_out => core_clk156_out,
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core_clk156_out => core_clk156_out,
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qplloutclk_out => qplloutclk_out,
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txp => gtx10g_txp(n),
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qplloutrefclk_out => qplloutrefclk_out,
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txn => gtx10g_txn(n),
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qplllock_out => qplllock_out,
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rxp => gtx10g_rxp(n),
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rxn => gtx10g_rxn(n),
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txusrclk_out => s_txusrclk_out,
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txusrclk_out => s_txusrclk_out,
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txusrclk2_out => s_txusrclk2_out,
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txusrclk2_out => s_txusrclk2_out,
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areset_clk156_out => areset_clk156_out,
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areset_datapathclk_out => areset_clk156_out,
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gttxreset_out => gttxreset_out,
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gttxreset_out => gttxreset_out,
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gtrxreset_out => gtrxreset_out,
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gtrxreset_out => gtrxreset_out,
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txuserrdy_out => txuserrdy_out,
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txuserrdy_out => txuserrdy_out,
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reset_counter_done_out => reset_counter_done_out,
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reset_counter_done_out => reset_counter_done_out,
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qplllock_out => qplllock_out,
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reset => reset,
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qplloutclk_out => qplloutclk_out,
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gt0_eyescanreset => '0',
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qplloutrefclk_out => qplloutrefclk_out,
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gt0_eyescantrigger => '0',
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gt0_rxcdrhold => '0',
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gt0_txprbsforceerr => '0',
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gt0_txpolarity => '0',
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gt0_rxpolarity => '0',
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gt0_rxrate => (others => '0'),
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gt0_txpmareset => '0',
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gt0_rxpmareset => '0',
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gt0_rxdfelpmreset => '0',
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gt0_txprecursor => (others => '0'),
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gt0_txpostcursor => (others => '0'),
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gt0_txdiffctrl => "1110",
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gt0_rxlpmen => '0',
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gt0_eyescandataerror => open,
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gt0_txbufstatus => open,
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gt0_txresetdone => open,
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gt0_rxresetdone => open,
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gt0_rxbufstatus => open,
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gt0_rxprbserr => open,
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gt0_dmonitorout => open,
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xgmii_txd => xgmii_txd(n),
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xgmii_txd => xgmii_txd(n),
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xgmii_txc => xgmii_txc(n),
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xgmii_txc => xgmii_txc(n),
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xgmii_rxd => xgmii_rxd(n),
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xgmii_rxd => xgmii_rxd(n),
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xgmii_rxc => xgmii_rxc(n),
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xgmii_rxc => xgmii_rxc(n),
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txp => gtx10g_txp(n),
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txn => gtx10g_txn(n),
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rxp => gtx10g_rxp(n),
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rxn => gtx10g_rxn(n),
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configuration_vector => configuration_vector,
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configuration_vector => configuration_vector,
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status_vector => status_vector(n),
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status_vector => status_vector(n),
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core_status => core_status(n),
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core_status => core_status(n),
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resetdone_out => s_resetdone,
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signal_detect => signal_detect(n),
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signal_detect => signal_detect(n),
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tx_fault => tx_fault(n),
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tx_fault => tx_fault(n),
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drp_req => drp_req(n),
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drp_req => drp_req(n),
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drp_gnt => drp_gnt(n),
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drp_gnt => drp_gnt(n),
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drp_den_o => drp_den_o(n),
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drp_den_o => drp_den_o(n),
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drp_dwe_o => drp_dwe_o(n),
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drp_dwe_o => drp_dwe_o(n),
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drp_daddr_o => drp_daddr_o(n),
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drp_daddr_o => drp_daddr_o(n),
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drp_di_o => drp_di_o(n),
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drp_di_o => drp_di_o(n),
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drp_drdy_o => drp_drdy_o(n),
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drp_drdy_i => drp_drdy_i(n),
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drp_drpdo_o => drp_drpdo_o(n),
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drp_drpdo_i => drp_drpdo_i(n),
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drp_den_i => drp_den_i(n),
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drp_den_i => drp_den_i(n),
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drp_dwe_i => drp_dwe_i(n),
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drp_dwe_i => drp_dwe_i(n),
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drp_daddr_i => drp_daddr_i(n),
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drp_daddr_i => drp_daddr_i(n),
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drp_di_i => drp_di_i(n),
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drp_di_i => drp_di_i(n),
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drp_drdy_i => drp_drdy_i(n),
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drp_drdy_o => drp_drdy_o(n),
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drp_drpdo_i => drp_drpdo_i(n),
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drp_drpdo_o => drp_drpdo_o(n),
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tx_disable => tx_disable(n),
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pma_pmd_type => "111",
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pma_pmd_type => "111",
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gt0_eyescanreset => '0',
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tx_disable => tx_disable(n)
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gt0_eyescandataerror => open,
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gt0_txbufstatus => open,
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gt0_rxbufstatus => open,
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gt0_eyescantrigger => '0',
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gt0_rxcdrhold => '0',
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gt0_txprbsforceerr => '0',
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gt0_txpolarity => '0',
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gt0_rxpolarity => '0',
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gt0_rxprbserr => open,
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gt0_txpmareset => '0',
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gt0_rxpmareset => '0',
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gt0_txresetdone => open,
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gt0_rxresetdone => open,
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gt0_rxdfelpmreset => '0',
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gt0_rxlpmen => '0',
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gt0_dmonitorout => open,
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gt0_rxrate => (others => '0'),
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gt0_txprecursor => (others => '0'),
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gt0_txpostcursor => (others => '0'),
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gt0_txdiffctrl => "1110"
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);
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);
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end generate il1;
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end generate il1;
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il2 : if n /= 0 generate
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il2 : if n /= 0 generate
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ten_gig_eth_pcs_pma_1_1 : entity work.ten_gig_eth_pcs_pma_1
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ten_gig_eth_pcs_pma_1_1 : ten_gig_eth_pcs_pma_1
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port map (
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port map (
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dclk => clk_user,
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dclk => clk_user,
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clk156 => core_clk156_out,
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rxrecclk_out => open, --??
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coreclk => core_clk156_out,
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txusrclk => s_txusrclk_out,
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txusrclk => s_txusrclk_out,
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txusrclk2 => s_txusrclk2_out,
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txusrclk2 => s_txusrclk2_out,
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txclk322 => open,
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txoutclk => open,
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areset => reset,
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areset => reset,
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areset_clk156 => areset_clk156_out,
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areset_coreclk => areset_clk156_out,
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gttxreset => gttxreset_out,
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gttxreset => gttxreset_out,
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gtrxreset => gtrxreset_out,
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gtrxreset => gtrxreset_out,
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sim_speedup_control => '0',
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sim_speedup_control => '0',
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txuserrdy => txuserrdy_out,
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txuserrdy => txuserrdy_out,
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qplllock => qplllock_out,
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qplllock => qplllock_out,
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