| Line 37... |
Line 37... |
|
|
type T_HB is array (0 to 2) of integer;
|
type T_HB is array (0 to 2) of integer;
|
signal heart_bit : T_HB := (0, 0, 0);
|
signal heart_bit : T_HB := (0, 0, 0);
|
signal s_hb_led : std_logic_vector(2 downto 0) := "000";
|
signal s_hb_led : std_logic_vector(2 downto 0) := "000";
|
|
|
signal refclk_p : std_logic_vector(N_OF_QUADS-1 downto 0) := "00";
|
signal refclk_p : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
|
signal refclk_n : std_logic_vector(N_OF_QUADS-1 downto 0) := "00";
|
signal refclk_n : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
|
signal reset : std_logic := '0';
|
signal reset : std_logic := '0';
|
signal rst_p : std_logic := '1'; -- generated reset
|
signal rst_p : std_logic := '1'; -- generated reset
|
signal rst_cnt : integer := 20000000;
|
signal rst_cnt : integer := 20000000;
|
|
|
type T_FRQ_CNT is array (0 to 1) of std_logic_vector(31 downto 0);
|
type T_FRQ_CNT is array (0 to 1) of std_logic_vector(31 downto 0);
|
signal frq_user : T_FRQ_CNT := (others => (others => '0'));
|
signal frq_user : T_FRQ_CNT := (others => (others => '0'));
|
signal clk0_frq, clk1_frq : std_logic_vector(31 downto 0) := (others=>'0');
|
signal clk0_frq, clk1_frq : std_logic_vector(31 downto 0) := (others=>'0');
|
|
|
signal s_resetdone : std_logic_vector(N_OF_QUADS-1 downto 0) := "00";
|
signal s_resetdone : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
|
signal core_clk156_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00";
|
signal core_clk156_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
|
|
|
|
|
type T_MAC_TABLE is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(47 downto 0);
|
type T_MAC_TABLE is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(47 downto 0);
|
constant mac_table : T_MAC_TABLE := (
|
constant mac_table : T_MAC_TABLE := (
|
0 => x"de_ad_fa_de_00_e2",
|
0 => x"de_ad_fa_de_00_e2",
|
| Line 63... |
Line 63... |
5 => x"de_ad_fa_de_05_e2",
|
5 => x"de_ad_fa_de_05_e2",
|
6 => x"de_ad_fa_de_06_e2",
|
6 => x"de_ad_fa_de_06_e2",
|
7 => x"de_ad_fa_de_07_e2"
|
7 => x"de_ad_fa_de_07_e2"
|
);
|
);
|
|
|
signal s_txusrclk_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00";
|
signal s_txusrclk_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
|
signal s_txusrclk2_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00";
|
signal s_txusrclk2_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
|
signal areset_clk156_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00";
|
signal areset_clk156_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
|
signal gttxreset_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00";
|
signal gttxreset_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
|
signal gtrxreset_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00";
|
signal gtrxreset_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
|
signal txuserrdy_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00";
|
signal txuserrdy_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
|
signal reset_counter_done_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00";
|
signal reset_counter_done_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
|
signal qplllock_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00";
|
signal qplllock_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
|
signal qplloutclk_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00";
|
signal qplloutclk_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
|
signal qplloutrefclk_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00";
|
signal qplloutrefclk_out : std_logic_vector(N_OF_QUADS-1 downto 0) := (others => '0');
|
type T_XGMII_XD is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(63 downto 0);
|
type T_XGMII_XD is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(63 downto 0);
|
signal xgmii_txd : T_XGMII_XD := (others => (others => '0'));
|
signal xgmii_txd : T_XGMII_XD := (others => (others => '0'));
|
type T_XGMII_XC is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(7 downto 0);
|
type T_XGMII_XC is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(7 downto 0);
|
signal xgmii_txc : T_XGMII_XC := (others => (others => '0'));
|
signal xgmii_txc : T_XGMII_XC := (others => (others => '0'));
|
signal xgmii_rxd : T_XGMII_XD := (others => (others => '0'));
|
signal xgmii_rxd : T_XGMII_XD := (others => (others => '0'));
|
| Line 114... |
Line 114... |
signal clk_user : std_logic_vector(N_OF_QUADS-1 downto 0);
|
signal clk_user : std_logic_vector(N_OF_QUADS-1 downto 0);
|
|
|
component ten_gig_eth_pcs_pma_0 is
|
component ten_gig_eth_pcs_pma_0 is
|
port (
|
port (
|
dclk : in std_logic;
|
dclk : in std_logic;
|
|
rxrecclk_out : out std_logic;
|
refclk_p : in std_logic;
|
refclk_p : in std_logic;
|
refclk_n : in std_logic;
|
refclk_n : in std_logic;
|
sim_speedup_control : in std_logic;
|
sim_speedup_control : in std_logic;
|
core_clk156_out : out std_logic;
|
coreclk_out : out std_logic;
|
qplloutclk_out : out std_logic;
|
qplloutclk_out : out std_logic;
|
qplloutrefclk_out : out std_logic;
|
qplloutrefclk_out : out std_logic;
|
qplllock_out : out std_logic;
|
qplllock_out : out std_logic;
|
txusrclk_out : out std_logic;
|
txusrclk_out : out std_logic;
|
txusrclk2_out : out std_logic;
|
txusrclk2_out : out std_logic;
|
areset_clk156_out : out std_logic;
|
areset_datapathclk_out : out std_logic;
|
gttxreset_out : out std_logic;
|
gttxreset_out : out std_logic;
|
gtrxreset_out : out std_logic;
|
gtrxreset_out : out std_logic;
|
txuserrdy_out : out std_logic;
|
txuserrdy_out : out std_logic;
|
reset_counter_done_out : out std_logic;
|
reset_counter_done_out : out std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
| Line 161... |
Line 162... |
rxp : in std_logic;
|
rxp : in std_logic;
|
rxn : in std_logic;
|
rxn : in std_logic;
|
configuration_vector : in std_logic_vector (535 downto 0);
|
configuration_vector : in std_logic_vector (535 downto 0);
|
status_vector : out std_logic_vector (447 downto 0);
|
status_vector : out std_logic_vector (447 downto 0);
|
core_status : out std_logic_vector (7 downto 0);
|
core_status : out std_logic_vector (7 downto 0);
|
resetdone : out std_logic;
|
resetdone_out : out std_logic;
|
signal_detect : in std_logic;
|
signal_detect : in std_logic;
|
tx_fault : in std_logic;
|
tx_fault : in std_logic;
|
drp_req : out std_logic;
|
drp_req : out std_logic;
|
drp_gnt : in std_logic;
|
drp_gnt : in std_logic;
|
drp_den_o : out std_logic;
|
drp_den_o : out std_logic;
|
| Line 185... |
Line 186... |
end component ten_gig_eth_pcs_pma_0;
|
end component ten_gig_eth_pcs_pma_0;
|
|
|
component ten_gig_eth_pcs_pma_1 is
|
component ten_gig_eth_pcs_pma_1 is
|
port (
|
port (
|
dclk : in std_logic;
|
dclk : in std_logic;
|
clk156 : in std_logic;
|
rxrecclk_out : out std_logic;
|
|
coreclk : in std_logic;
|
txusrclk : in std_logic;
|
txusrclk : in std_logic;
|
txusrclk2 : in std_logic;
|
txusrclk2 : in std_logic;
|
txclk322 : out std_logic;
|
txoutclk : out std_logic;
|
areset : in std_logic;
|
areset : in std_logic;
|
areset_clk156 : in std_logic;
|
areset_coreclk : in std_logic;
|
gttxreset : in std_logic;
|
gttxreset : in std_logic;
|
gtrxreset : in std_logic;
|
gtrxreset : in std_logic;
|
sim_speedup_control : in std_logic;
|
sim_speedup_control : in std_logic;
|
txuserrdy : in std_logic;
|
txuserrdy : in std_logic;
|
qplllock : in std_logic;
|
qplllock : in std_logic;
|
| Line 327... |
Line 329... |
|
|
gl1 : for q in 0 to N_OF_QUADS-1 generate
|
gl1 : for q in 0 to N_OF_QUADS-1 generate
|
gl2 : for n in 0 to N_OF_LINKS-1 generate
|
gl2 : for n in 0 to N_OF_LINKS-1 generate
|
|
|
il1 : if n = 0 generate
|
il1 : if n = 0 generate
|
|
|
ten_gig_eth_pcs_pma_0_1 : ten_gig_eth_pcs_pma_0
|
ten_gig_eth_pcs_pma_0_1 : ten_gig_eth_pcs_pma_0
|
port map (
|
port map (
|
dclk => core_clk156_out(q),
|
dclk => core_clk156_out(q),
|
sim_speedup_control => '0',
|
rxrecclk_out => open, --??
|
refclk_p => refclk_p(q),
|
refclk_p => refclk_p(q),
|
refclk_n => refclk_n(q),
|
refclk_n => refclk_n(q),
|
reset => reset,
|
sim_speedup_control => '0',
|
resetdone => s_resetdone(q),
|
coreclk_out => core_clk156_out(q),
|
core_clk156_out => core_clk156_out(q),
|
qplloutclk_out => qplloutclk_out(q),
|
txp => gtx10g_txp(q*N_OF_LINKS+n),
|
qplloutrefclk_out => qplloutrefclk_out(q),
|
txn => gtx10g_txn(q*N_OF_LINKS+n),
|
qplllock_out => qplllock_out(q),
|
rxp => gtx10g_rxp(q*N_OF_LINKS+n),
|
|
rxn => gtx10g_rxn(q*N_OF_LINKS+n),
|
|
txusrclk_out => s_txusrclk_out(q),
|
txusrclk_out => s_txusrclk_out(q),
|
txusrclk2_out => s_txusrclk2_out(q),
|
txusrclk2_out => s_txusrclk2_out(q),
|
areset_clk156_out => areset_clk156_out(q),
|
areset_datapathclk_out => areset_clk156_out(q),
|
gttxreset_out => gttxreset_out(q),
|
gttxreset_out => gttxreset_out(q),
|
gtrxreset_out => gtrxreset_out(q),
|
gtrxreset_out => gtrxreset_out(q),
|
txuserrdy_out => txuserrdy_out(q),
|
txuserrdy_out => txuserrdy_out(q),
|
reset_counter_done_out => reset_counter_done_out(q),
|
reset_counter_done_out => reset_counter_done_out(q),
|
qplllock_out => qplllock_out(q),
|
reset => reset,
|
qplloutclk_out => qplloutclk_out(q),
|
gt0_eyescanreset => '0',
|
qplloutrefclk_out => qplloutrefclk_out(q),
|
gt0_eyescantrigger => '0',
|
|
gt0_rxcdrhold => '0',
|
|
gt0_txprbsforceerr => '0',
|
|
gt0_txpolarity => '0',
|
|
gt0_rxpolarity => '0',
|
|
gt0_rxrate => (others => '0'),
|
|
gt0_txpmareset => '0',
|
|
gt0_rxpmareset => '0',
|
|
gt0_rxdfelpmreset => '0',
|
|
gt0_txprecursor => (others => '0'),
|
|
gt0_txpostcursor => (others => '0'),
|
|
gt0_txdiffctrl => "1110",
|
|
gt0_rxlpmen => '0',
|
|
gt0_eyescandataerror => open,
|
|
gt0_txbufstatus => open,
|
|
gt0_txresetdone => open,
|
|
gt0_rxresetdone => open,
|
|
gt0_rxbufstatus => open,
|
|
gt0_rxprbserr => open,
|
|
gt0_dmonitorout => open,
|
xgmii_txd => xgmii_txd(q*N_OF_LINKS+n),
|
xgmii_txd => xgmii_txd(q*N_OF_LINKS+n),
|
xgmii_txc => xgmii_txc(q*N_OF_LINKS+n),
|
xgmii_txc => xgmii_txc(q*N_OF_LINKS+n),
|
xgmii_rxd => xgmii_rxd(q*N_OF_LINKS+n),
|
xgmii_rxd => xgmii_rxd(q*N_OF_LINKS+n),
|
xgmii_rxc => xgmii_rxc(q*N_OF_LINKS+n),
|
xgmii_rxc => xgmii_rxc(q*N_OF_LINKS+n),
|
|
txp => gtx10g_txp(q*N_OF_LINKS+n),
|
|
txn => gtx10g_txn(q*N_OF_LINKS+n),
|
|
rxp => gtx10g_rxp(q*N_OF_LINKS+n),
|
|
rxn => gtx10g_rxn(q*N_OF_LINKS+n),
|
configuration_vector => configuration_vector,
|
configuration_vector => configuration_vector,
|
status_vector => status_vector(q*N_OF_LINKS+n),
|
status_vector => status_vector(q*N_OF_LINKS+n),
|
core_status => core_status(q*N_OF_LINKS+n),
|
core_status => core_status(q*N_OF_LINKS+n),
|
|
resetdone_out => s_resetdone(q),
|
signal_detect => signal_detect(q*N_OF_LINKS+n),
|
signal_detect => signal_detect(q*N_OF_LINKS+n),
|
tx_fault => tx_fault(q*N_OF_LINKS+n),
|
tx_fault => tx_fault(q*N_OF_LINKS+n),
|
drp_req => drp_req(q*N_OF_LINKS+n),
|
drp_req => drp_req(q*N_OF_LINKS+n),
|
drp_gnt => drp_gnt(q*N_OF_LINKS+n),
|
drp_gnt => drp_gnt(q*N_OF_LINKS+n),
|
drp_den_o => drp_den_o(q*N_OF_LINKS+n),
|
drp_den_o => drp_den_o(q*N_OF_LINKS+n),
|
drp_dwe_o => drp_dwe_o(q*N_OF_LINKS+n),
|
drp_dwe_o => drp_dwe_o(q*N_OF_LINKS+n),
|
drp_daddr_o => drp_daddr_o(q*N_OF_LINKS+n),
|
drp_daddr_o => drp_daddr_o(q*N_OF_LINKS+n),
|
drp_di_o => drp_di_o(q*N_OF_LINKS+n),
|
drp_di_o => drp_di_o(q*N_OF_LINKS+n),
|
drp_drdy_o => drp_drdy_o(q*N_OF_LINKS+n),
|
drp_drdy_i => drp_drdy_i(q*N_OF_LINKS+n),
|
drp_drpdo_o => drp_drpdo_o(q*N_OF_LINKS+n),
|
drp_drpdo_i => drp_drpdo_i(q*N_OF_LINKS+n),
|
drp_den_i => drp_den_i(q*N_OF_LINKS+n),
|
drp_den_i => drp_den_i(q*N_OF_LINKS+n),
|
drp_dwe_i => drp_dwe_i(q*N_OF_LINKS+n),
|
drp_dwe_i => drp_dwe_i(q*N_OF_LINKS+n),
|
drp_daddr_i => drp_daddr_i(q*N_OF_LINKS+n),
|
drp_daddr_i => drp_daddr_i(q*N_OF_LINKS+n),
|
drp_di_i => drp_di_i(q*N_OF_LINKS+n),
|
drp_di_i => drp_di_i(q*N_OF_LINKS+n),
|
drp_drdy_i => drp_drdy_i(q*N_OF_LINKS+n),
|
drp_drdy_o => drp_drdy_o(q*N_OF_LINKS+n),
|
drp_drpdo_i => drp_drpdo_i(q*N_OF_LINKS+n),
|
drp_drpdo_o => drp_drpdo_o(q*N_OF_LINKS+n),
|
tx_disable => tx_disable(q*N_OF_LINKS+n),
|
|
pma_pmd_type => "111",
|
pma_pmd_type => "111",
|
gt0_eyescanreset => '0',
|
tx_disable => tx_disable(q*N_OF_LINKS+n)
|
gt0_eyescandataerror => open,
|
|
gt0_txbufstatus => open,
|
|
gt0_rxbufstatus => open,
|
|
gt0_eyescantrigger => '0',
|
|
gt0_rxcdrhold => '0',
|
|
gt0_txprbsforceerr => '0',
|
|
gt0_txpolarity => '0',
|
|
gt0_rxpolarity => '0',
|
|
gt0_rxprbserr => open,
|
|
gt0_txpmareset => '0',
|
|
gt0_rxpmareset => '0',
|
|
gt0_txresetdone => open,
|
|
gt0_rxresetdone => open,
|
|
gt0_rxdfelpmreset => '0',
|
|
gt0_rxlpmen => '0',
|
|
gt0_dmonitorout => open,
|
|
gt0_rxrate => (others => '0'),
|
|
gt0_txprecursor => (others => '0'),
|
|
gt0_txpostcursor => (others => '0'),
|
|
gt0_txdiffctrl => "1110"
|
|
|
|
);
|
);
|
|
|
end generate il1;
|
end generate il1;
|
il2 : if n /= 0 generate
|
il2 : if n /= 0 generate
|
ten_gig_eth_pcs_pma_1_1 : entity work.ten_gig_eth_pcs_pma_1
|
ten_gig_eth_pcs_pma_1_1 : entity work.ten_gig_eth_pcs_pma_1
|
port map (
|
port map (
|
dclk => core_clk156_out(q),
|
dclk => core_clk156_out(q),
|
clk156 => core_clk156_out(q),
|
rxrecclk_out => open, --??
|
|
coreclk => core_clk156_out(q),
|
txusrclk => s_txusrclk_out(q),
|
txusrclk => s_txusrclk_out(q),
|
txusrclk2 => s_txusrclk2_out(q),
|
txusrclk2 => s_txusrclk2_out(q),
|
txclk322 => open,
|
|
areset => reset,
|
areset => reset,
|
areset_clk156 => areset_clk156_out(q),
|
areset_coreclk => areset_clk156_out(q),
|
gttxreset => gttxreset_out(q),
|
gttxreset => gttxreset_out(q),
|
gtrxreset => gtrxreset_out(q),
|
gtrxreset => gtrxreset_out(q),
|
sim_speedup_control => '0',
|
sim_speedup_control => '0',
|
txuserrdy => txuserrdy_out(q),
|
txuserrdy => txuserrdy_out(q),
|
qplllock => qplllock_out(q),
|
qplllock => qplllock_out(q),
|
| Line 541... |
Line 544... |
port map (
|
port map (
|
clk => boot_clk,
|
clk => boot_clk,
|
scl => scl,
|
scl => scl,
|
sda => sda);
|
sda => sda);
|
|
|
gld1 : for i in 0 to 1 generate
|
gld1 : for i in 0 to N_OF_QUADS-1 generate
|
p1 : process (clk_user(i), rst_n)
|
p1 : process (clk_user(i), rst_n)
|
begin -- process p1
|
begin -- process p1
|
if rst_n = '0' then -- asynchronous reset (active low)
|
if rst_n = '0' then -- asynchronous reset (active low)
|
heart_bit(i) <= 0;
|
heart_bit(i) <= 0;
|
elsif clk_user(i)'event and clk_user(i) = '1' then -- rising clock edge
|
elsif clk_user(i)'event and clk_user(i) = '1' then -- rising clock edge
|
