| Line 5... |
Line 5... |
-- File : atlys_eth_top.vhd
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-- File : atlys_eth_top.vhd
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-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
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-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
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-- License : BSD License
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-- License : BSD License
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-- Company :
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-- Company :
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-- Created : 2010-08-03
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-- Created : 2010-08-03
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-- Last update: 2014-10-20
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-- Last update: 2014-11-15
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-- Platform :
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-- Platform :
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-- Standard : VHDL
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-- Standard : VHDL
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description:
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-- Description:
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-- This file implements the top entity, integrating all component
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-- This file implements the top entity, integrating all component
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| Line 181... |
Line 181... |
cmd_arg : out std_logic_vector(31 downto 0);
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cmd_arg : out std_logic_vector(31 downto 0);
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cmd_run : out std_logic;
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cmd_run : out std_logic;
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cmd_retr_s : out std_logic;
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cmd_retr_s : out std_logic;
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cmd_ack : in std_logic;
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cmd_ack : in std_logic;
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cmd_response_in : in std_logic_vector(8*12-1 downto 0);
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cmd_response_in : in std_logic_vector(8*12-1 downto 0);
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retr_count : out std_logic_vector(31 downto 0);
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transmit_data : in std_logic;
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transmit_data : in std_logic;
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transm_delay : out unsigned(31 downto 0);
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transm_delay : out unsigned(31 downto 0);
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dbg : out std_logic_vector(3 downto 0);
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dbg : out std_logic_vector(3 downto 0);
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clk : in std_logic;
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clk : in std_logic;
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rst_n : in std_logic);
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rst_n : in std_logic);
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| Line 197... |
Line 198... |
cmd_arg : in std_logic_vector(31 downto 0);
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cmd_arg : in std_logic_vector(31 downto 0);
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cmd_run : in std_logic;
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cmd_run : in std_logic;
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cmd_ack : out std_logic;
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cmd_ack : out std_logic;
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cmd_response : out std_logic_vector(8*12-1 downto 0);
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cmd_response : out std_logic_vector(8*12-1 downto 0);
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clk : in std_logic;
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clk : in std_logic;
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rst_p : in std_logic);
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rst_p : in std_logic;
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retr_count : in std_logic_vector(31 downto 0)
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);
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end component cmd_proc;
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end component cmd_proc;
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component eth_sender is
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component eth_sender is
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port (
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port (
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peer_mac : in std_logic_vector(47 downto 0);
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peer_mac : in std_logic_vector(47 downto 0);
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| Line 353... |
Line 356... |
signal cmd_ack : std_logic := '0';
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signal cmd_ack : std_logic := '0';
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signal cmd_code : std_logic_vector(15 downto 0) := (others => '0');
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signal cmd_code : std_logic_vector(15 downto 0) := (others => '0');
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signal cmd_seq : std_logic_vector(15 downto 0) := (others => '0');
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signal cmd_seq : std_logic_vector(15 downto 0) := (others => '0');
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signal cmd_arg : std_logic_vector(31 downto 0) := (others => '0');
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signal cmd_arg : std_logic_vector(31 downto 0) := (others => '0');
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|
|
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signal retr_count : std_logic_vector(31 downto 0);
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begin -- beh
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begin -- beh
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|
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-- Allow selection of MAC with the DIP switch to allow testing
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-- Allow selection of MAC with the DIP switch to allow testing
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-- with multiple boards!
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-- with multiple boards!
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| Line 429... |
Line 433... |
cmd_arg => cmd_arg,
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cmd_arg => cmd_arg,
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cmd_run => cmd_run,
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cmd_run => cmd_run,
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cmd_retr_s => cmd_retr_s,
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cmd_retr_s => cmd_retr_s,
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cmd_ack => cmd_ack,
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cmd_ack => cmd_ack,
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cmd_response_in => cmd_response_in,
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cmd_response_in => cmd_response_in,
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retr_count => retr_count,
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transmit_data => transmit_data,
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transmit_data => transmit_data,
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transm_delay => transm_delay,
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transm_delay => transm_delay,
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dbg => dbg,
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dbg => dbg,
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clk => clk_user,
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clk => clk_user,
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rst_n => rst_n);
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rst_n => rst_n);
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| Line 444... |
Line 449... |
cmd_arg => cmd_arg,
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cmd_arg => cmd_arg,
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cmd_run => cmd_run,
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cmd_run => cmd_run,
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cmd_ack => cmd_ack,
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cmd_ack => cmd_ack,
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cmd_response => cmd_response_in,
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cmd_response => cmd_response_in,
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clk => clk_user,
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clk => clk_user,
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rst_p => rst_p);
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rst_p => rst_p,
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retr_count => retr_count
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);
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eth_sender_1 : eth_sender
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eth_sender_1 : eth_sender
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port map (
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port map (
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peer_mac => peer_mac,
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peer_mac => peer_mac,
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my_mac => my_mac,
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my_mac => my_mac,
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