Line 5... |
Line 5... |
unknown
|
unknown
|
1.0
|
1.0
|
|
|
|
|
ack_fifo
|
ack_fifo
|
|
|
|
|
ack_fifo
|
100000000
|
Independent_Clocks_Block_RAM
|
100000000
|
2
|
100000000
|
2
|
100000000
|
Native
|
100000000
|
First_Word_Fall_Through
|
0
|
false
|
0
|
64
|
0
|
512
|
0
|
64
|
0
|
512
|
0
|
false
|
0
|
false
|
8
|
true
|
1
|
true
|
1
|
Asynchronous_Reset
|
1
|
1
|
1
|
true
|
4
|
0
|
0
|
false
|
32
|
false
|
1
|
false
|
1
|
false
|
1
|
Active_High
|
64
|
false
|
1
|
Active_High
|
8
|
false
|
1
|
Active_High
|
1
|
false
|
1
|
Active_High
|
1
|
false
|
|
false
|
|
false
|
|
false
|
|
false
|
|
9
|
|
false
|
|
9
|
|
false
|
|
9
|
|
false
|
|
1
|
|
1
|
|
No_Programmable_Full_Threshold
|
|
511
|
|
510
|
|
No_Programmable_Empty_Threshold
|
|
4
|
|
5
|
|
AXI4
|
|
Common_Clock
|
|
false
|
|
Slave_Interface_Clock_Enable
|
|
READ_WRITE
|
|
0
|
|
32
|
|
64
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
1
|
|
0
|
|
0
|
|
4
|
|
true
|
|
false
|
|
false
|
|
1
|
|
false
|
|
1
|
|
FIFO
|
|
Common_Clock_Block_RAM
|
|
Data_FIFO
|
|
false
|
|
false
|
|
false
|
|
16
|
|
false
|
|
No_Programmable_Full_Threshold
|
|
1023
|
|
No_Programmable_Empty_Threshold
|
|
1022
|
|
FIFO
|
|
Common_Clock_Block_RAM
|
|
Data_FIFO
|
|
false
|
|
false
|
|
false
|
|
1024
|
|
false
|
|
No_Programmable_Full_Threshold
|
|
1023
|
|
No_Programmable_Empty_Threshold
|
|
1022
|
|
FIFO
|
|
Common_Clock_Block_RAM
|
|
Data_FIFO
|
|
false
|
|
false
|
|
false
|
|
16
|
|
false
|
|
No_Programmable_Full_Threshold
|
|
1023
|
|
No_Programmable_Empty_Threshold
|
|
1022
|
|
FIFO
|
|
Common_Clock_Block_RAM
|
|
Data_FIFO
|
|
false
|
|
false
|
|
false
|
|
16
|
|
false
|
|
No_Programmable_Full_Threshold
|
|
1023
|
|
No_Programmable_Empty_Threshold
|
|
1022
|
|
FIFO
|
|
Common_Clock_Block_RAM
|
|
Data_FIFO
|
|
false
|
|
false
|
|
false
|
|
1024
|
|
false
|
|
No_Programmable_Full_Threshold
|
|
1023
|
|
No_Programmable_Empty_Threshold
|
|
1022
|
|
FIFO
|
|
Common_Clock_Block_RAM
|
|
Data_FIFO
|
|
false
|
|
false
|
|
false
|
|
1024
|
|
false
|
|
No_Programmable_Full_Threshold
|
|
1023
|
|
No_Programmable_Empty_Threshold
|
|
1022
|
|
Fully_Registered
|
|
Fully_Registered
|
|
Fully_Registered
|
|
Fully_Registered
|
|
Fully_Registered
|
|
Fully_Registered
|
|
false
|
|
Active_High
|
|
false
|
|
Active_High
|
|
false
|
|
false
|
|
false
|
|
false
|
|
false
|
|
false
|
|
false
|
|
false
|
|
0
|
0
|
0
|
0
|
9
|
9
|
BlankString
|
BlankString
|
64
|
64
|
|
1
|
|
32
|
|
64
|
|
1
|
|
64
|
|
2
|
0
|
0
|
64
|
64
|
0
|
0
|
|
1
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
kintex7
|
kintex7
|
1
|
1
|
0
|
0
|
0
|
0
|
|
1
|
|
0
|
|
0
|
|
0
|
|
0
|
|
1
|
|
0
|
|
1
|
|
0
|
|
0
|
|
0
|
|
0
|
|
1
|
|
0
|
|
1
|
|
0
|
0
|
0
|
0
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
0
|
0
|
|
0
|
0
|
0
|
0
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
0
|
0
|
0
|
0
|
1
|
1
|
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
2
|
2
|
|
1
|
|
1
|
|
1
|
|
1
|
|
1
|
|
1
|
0
|
0
|
|
0
|
1
|
1
|
BlankString
|
BlankString
|
|
1
|
0
|
0
|
0
|
0
|
|
0
|
0
|
0
|
1
|
1
|
512x72
|
512x72
|
|
1kx18
|
|
512x36
|
|
1kx36
|
|
512x36
|
|
1kx36
|
|
512x36
|
4
|
4
|
|
1022
|
|
1022
|
|
1022
|
|
1022
|
|
1022
|
|
1022
|
5
|
5
|
0
|
0
|
511
|
0
|
510
|
0
|
0
|
0
|
9
|
0
|
512
|
0
|
|
0
|
|
511
|
|
1023
|
|
1023
|
|
1023
|
|
1023
|
|
1023
|
|
1023
|
|
510
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
9
|
|
512
|
1
|
1
|
9
|
9
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
2
|
0
|
0
|
|
0
|
|
0
|
|
0
|
1
|
1
|
0
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
0
|
0
|
0
|
|
0
|
|
0
|
0
|
0
|
0
|
|
0
|
0
|
0
|
0
|
|
9
|
|
512
|
|
1
|
|
9
|
|
1
|
|
1
|
|
1
|
|
0
|
|
2
|
|
0
|
|
1
|
|
1
|
|
1
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
1
|
|
32
|
|
64
|
|
8
|
|
1
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
1
|
|
1
|
|
1
|
|
1
|
|
1
|
|
1
|
|
0
|
|
0
|
|
1
|
|
1
|
|
0
|
|
0
|
|
0
|
|
8
|
|
1
|
|
1
|
|
4
|
|
1
|
|
1
|
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
9
|
0
|
512
|
1
|
1024
|
1
|
16
|
1
|
1024
|
1
|
|
1
|
|
1
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
512x36
|
|
1kx36
|
|
512x36
|
|
512x36
|
|
1kx36
|
|
1kx18
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
0
|
|
32
|
|
64
|
|
2
|
|
32
|
|
64
|
|
1
|
|
16
|
16
|
1024
|
1024
|
16
|
16
|
16
|
1
|
1024
|
9
|
1024
|
10
|
|
4
|
|
10
|
4
|
4
|
10
|
10
|
4
|
4
|
4
|
1
|
10
|
32
|
10
|
0
|
0
|
0
|
0
|
false
|
0
|
false
|
0
|
false
|
0
|
0
|
0
|
0
|
0
|
Slave_Interface_Clock_Enable
|
0
|
Common_Clock
|
0
|
ack_fifo
|
0
|
64
|
0
|
false
|
0
|
9
|
0
|
false
|
0
|
false
|
0
|
0
|
0
|
4
|
0
|
1022
|
0
|
1022
|
1023
|
1022
|
1023
|
1022
|
1023
|
1022
|
1023
|
1022
|
1023
|
5
|
1023
|
false
|
0
|
false
|
0
|
false
|
0
|
false
|
0
|
false
|
0
|
false
|
0
|
false
|
1022
|
false
|
1022
|
false
|
1022
|
Hard_ECC
|
1022
|
false
|
1022
|
false
|
1022
|
false
|
0
|
false
|
0
|
false
|
0
|
false
|
0
|
true
|
0
|
false
|
0
|
false
|
|
true
|
|
Data_FIFO
|
|
Data_FIFO
|
|
Data_FIFO
|
|
Data_FIFO
|
|
Data_FIFO
|
|
Data_FIFO
|
|
Common_Clock_Block_RAM
|
|
Common_Clock_Block_RAM
|
|
Common_Clock_Block_RAM
|
|
Common_Clock_Block_RAM
|
|
Common_Clock_Block_RAM
|
|
Common_Clock_Block_RAM
|
|
Independent_Clocks_Block_RAM
|
|
1
|
|
511
|
|
1023
|
|
1023
|
|
1023
|
|
1023
|
|
1023
|
|
1023
|
|
510
|
|
false
|
|
false
|
|
false
|
|
0
|
|
Native
|
|
false
|
|
false
|
|
false
|
|
false
|
|
false
|
|
false
|
|
false
|
|
false
|
|
false
|
|
false
|
|
false
|
|
false
|
|
false
|
|
false
|
|
64
|
|
512
|
|
1024
|
|
16
|
|
1024
|
|
16
|
|
1024
|
|
16
|
|
false
|
|
64
|
|
512
|
|
Embedded_Reg
|
|
false
|
|
false
|
|
Active_High
|
|
Active_High
|
|
AXI4
|
|
First_Word_Fall_Through
|
|
No_Programmable_Empty_Threshold
|
|
No_Programmable_Empty_Threshold
|
|
No_Programmable_Empty_Threshold
|
|
No_Programmable_Empty_Threshold
|
|
No_Programmable_Empty_Threshold
|
|
No_Programmable_Empty_Threshold
|
|
No_Programmable_Empty_Threshold
|
|
No_Programmable_Full_Threshold
|
|
No_Programmable_Full_Threshold
|
|
No_Programmable_Full_Threshold
|
|
No_Programmable_Full_Threshold
|
|
No_Programmable_Full_Threshold
|
|
No_Programmable_Full_Threshold
|
|
No_Programmable_Full_Threshold
|
|
READ_WRITE
|
|
0
|
|
1
|
|
false
|
|
9
|
|
Fully_Registered
|
|
Fully_Registered
|
|
Fully_Registered
|
|
Fully_Registered
|
|
Fully_Registered
|
|
Fully_Registered
|
|
true
|
|
Asynchronous_Reset
|
|
false
|
|
1
|
|
0
|
|
0
|
|
1
|
|
1
|
|
4
|
|
false
|
|
false
|
|
Active_High
|
|
Active_High
|
|
true
|
|
false
|
|
false
|
|
false
|
|
false
|
|
Active_High
|
|
0
|
|
false
|
|
Active_High
|
|
1
|
|
false
|
|
9
|
|
false
|
|
FIFO
|
|
false
|
|
false
|
|
false
|
|
false
|
|
FIFO
|
|
FIFO
|
|
2
|
|
2
|
|
false
|
|
FIFO
|
|
FIFO
|
|
FIFO
|
kintex7
|
kintex7
|
|
xilinx.com:kc705:part0:0.9
|
xc7k325t
|
xc7k325t
|
ffg900
|
ffg900
|
-2
|
|
C
|
|
|
|
VHDL
|
VHDL
|
|
|
MIXED
|
MIXED
|
|
-2
|
|
|
TRUE
|
TRUE
|
TRUE
|
TRUE
|
xilinx.com:kc705:part0:0.9
|
IP_Flow
|
TRUE
|
|
2014.4
|
|
3
|
3
|
OUT_OF_CONTEXT
|
TRUE
|
|
|
.
|
.
|
|
|
.
|
.
|
|
2016.4
|
|
OUT_OF_CONTEXT
|
|
|
|
|
|
|
|
|