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[/] [fir_wishbone/] [trunk/] [tester/] [tb_fir.vhdl] - Diff between revs 10 and 11

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Line 29... Line 29...
*/
*/
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std.all;
 
 
entity tb_fir is generic(order:positive:=30; width:positive:=16);
entity tb_fir is generic(order:positive:=30);           --; width:positive:=16);
        port(
        port(
--              clk:in std_ulogic:='0';
--              clk:in std_ulogic:='0';
--              nRst:in std_ulogic:='0';
--              nRst:in std_ulogic:='0';
                --u:in signed(16-1 downto 0);
                --u:in signed(16-1 downto 0);
                y:out signed(16-1 downto 0)
                y:out signed(16-1 downto 0)
        );
        );
end entity tb_fir;
end entity tb_fir;
 
 
architecture rtl of tb_fir is
architecture rtl of tb_fir is
        signal reset:std_ulogic:='0';
        signal reset:std_ulogic:='0';
        signal u:signed(16-1 downto 0);
        signal u:signed(y'range);
        signal trig:std_logic;
        signal trig:std_logic;
 
 
        /* synthesis translate_off */
        /* synthesis translate_off */
        signal clk:std_ulogic:='0';
        signal clk:std_ulogic:='0';
        signal nRst:std_ulogic:='1';
        signal nRst:std_ulogic:='1';
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        /* Impulse generator for impulse response measurement. */
        /* Impulse generator for impulse response measurement. */
        u <= (0=>'1', others=>'0') when count=1 else (others=>'0');
        u <= (0=>'1', others=>'0') when count=1 else (others=>'0');
 
 
 
 
        filter: entity work.fir(rtl)
        filter: entity work.fir(rtl)
                generic map(order=>order, width=>width)
                generic map(order=>order)               --, width=>width)
                port map(
                port map(
                        reset=>reset,
                        reset=>reset,
                        clk=>clk,
                        clk=>clk,
 
 
                        /* Filter ports. */
                        /* Filter ports. */
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        /* Hardware debugger (SignalTap II embedded logic analyser). */
        /* Hardware debugger (SignalTap II embedded logic analyser). */
 
 
        trig<='1' when count<300 else '0';               -- Stop SignalTap Triggering after 300 counts, Total data=280
        trig<='1' when count<300 else '0';               -- Stop SignalTap Triggering after 300 counts, Total data=280
 
 
        /* SignalTap debugger. */
        /* SignalTap debugger. */
        dbgSignals(width-1 downto 0)<=std_ulogic_vector(u);                                              -- u:16bits
        dbgSignals(u'range)<=std_ulogic_vector(u);                                              -- u:16bits
        dbgSignals(width*2-1  downto width)<=std_ulogic_vector(y);                              -- y:32bits                                             
        dbgSignals(u'length*2-1  downto u'length)<=std_ulogic_vector(y);                                -- y:32bits                                             
        dbgSignals(8+width*2 downto width*2)<=std_ulogic_vector(count);         --9bits (300<512)
        dbgSignals(8+u'length*2 downto u'length*2)<=std_ulogic_vector(count);           --9bits (300<512)
 
 
/*      debugger: entity work.stp(syn) port map(
/*      debugger: entity work.stp(syn) port map(
                acq_clk=>clk,
                acq_clk=>clk,
                acq_data_in=>std_logic_vector(dbgSignals),              -- Type conversion: std_ulogic_vector --> std_logic_vector
                acq_data_in=>std_logic_vector(dbgSignals),              -- Type conversion: std_ulogic_vector --> std_logic_vector
                acq_trigger_in=>"1",
                acq_trigger_in=>"1",

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