| Line 29... |
Line 29... |
*/
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*/
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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|
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entity tb_fir is generic(order:positive:=30; width:positive:=16);
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entity tb_fir is generic(order:positive:=30); --; width:positive:=16);
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port(
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port(
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-- clk:in std_ulogic:='0';
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-- clk:in std_ulogic:='0';
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-- nRst:in std_ulogic:='0';
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-- nRst:in std_ulogic:='0';
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--u:in signed(16-1 downto 0);
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--u:in signed(16-1 downto 0);
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y:out signed(16-1 downto 0)
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y:out signed(16-1 downto 0)
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);
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);
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end entity tb_fir;
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end entity tb_fir;
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|
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architecture rtl of tb_fir is
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architecture rtl of tb_fir is
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signal reset:std_ulogic:='0';
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signal reset:std_ulogic:='0';
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signal u:signed(16-1 downto 0);
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signal u:signed(y'range);
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signal trig:std_logic;
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signal trig:std_logic;
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|
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/* synthesis translate_off */
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/* synthesis translate_off */
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signal clk:std_ulogic:='0';
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signal clk:std_ulogic:='0';
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signal nRst:std_ulogic:='1';
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signal nRst:std_ulogic:='1';
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| Line 89... |
Line 89... |
/* Impulse generator for impulse response measurement. */
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/* Impulse generator for impulse response measurement. */
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u <= (0=>'1', others=>'0') when count=1 else (others=>'0');
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u <= (0=>'1', others=>'0') when count=1 else (others=>'0');
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filter: entity work.fir(rtl)
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filter: entity work.fir(rtl)
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generic map(order=>order, width=>width)
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generic map(order=>order) --, width=>width)
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port map(
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port map(
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reset=>reset,
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reset=>reset,
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clk=>clk,
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clk=>clk,
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|
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/* Filter ports. */
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/* Filter ports. */
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| Line 125... |
Line 125... |
/* Hardware debugger (SignalTap II embedded logic analyser). */
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/* Hardware debugger (SignalTap II embedded logic analyser). */
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|
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trig<='1' when count<300 else '0'; -- Stop SignalTap Triggering after 300 counts, Total data=280
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trig<='1' when count<300 else '0'; -- Stop SignalTap Triggering after 300 counts, Total data=280
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|
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/* SignalTap debugger. */
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/* SignalTap debugger. */
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dbgSignals(width-1 downto 0)<=std_ulogic_vector(u); -- u:16bits
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dbgSignals(u'range)<=std_ulogic_vector(u); -- u:16bits
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dbgSignals(width*2-1 downto width)<=std_ulogic_vector(y); -- y:32bits
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dbgSignals(u'length*2-1 downto u'length)<=std_ulogic_vector(y); -- y:32bits
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dbgSignals(8+width*2 downto width*2)<=std_ulogic_vector(count); --9bits (300<512)
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dbgSignals(8+u'length*2 downto u'length*2)<=std_ulogic_vector(count); --9bits (300<512)
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|
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/* debugger: entity work.stp(syn) port map(
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/* debugger: entity work.stp(syn) port map(
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acq_clk=>clk,
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acq_clk=>clk,
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acq_data_in=>std_logic_vector(dbgSignals), -- Type conversion: std_ulogic_vector --> std_logic_vector
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acq_data_in=>std_logic_vector(dbgSignals), -- Type conversion: std_ulogic_vector --> std_logic_vector
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acq_trigger_in=>"1",
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acq_trigger_in=>"1",
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