| Line 22... |
Line 22... |
--
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--
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-- @note This file has been renamed and updated from the original.
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-- @note This file has been renamed and updated from the original.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.util.common_generics;
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package kbd_pkg is
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package kbd_pkg is
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component ps2_kbd_top is
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component ps2_kbd_top is
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generic(
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generic(
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clock_frequency: integer := 50000000; -- system clock frequency in hz
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clock_frequency: integer := 50000000; -- system clock frequency in Hz
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ps2_debounce_counter_size: integer := 8); -- set such that 2^size/clock_frequency = 5us (size = 8 for 50mhz)
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ps2_debounce_counter_size: integer := 8); -- set such that 2^size/clock_frequency = 5us (size = 8 for 50MHz)
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port(
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port(
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clk: in std_ulogic; -- system clock input
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clk: in std_ulogic; -- system clock input
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ps2_clk: in std_ulogic; -- clock signal from PS2 keyboard
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ps2_clk: in std_ulogic; -- clock signal from PS2 keyboard
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ps2_data: in std_ulogic; -- data signal from PS2 keyboard
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ps2_data: in std_ulogic; -- data signal from PS2 keyboard
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ascii_new: out std_ulogic := '0'; -- output flag indicating new ascii value
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ascii_new: out std_ulogic := '0'; -- output flag indicating new ascii value
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ascii_code: out std_ulogic_vector(6 downto 0)); -- ASCII value
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ascii_code: out std_ulogic_vector(6 downto 0)); -- ASCII value
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end component;
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end component;
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component ps2_kbd_core is
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component ps2_kbd_core is
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generic(
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generic(
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clock_frequency: integer := 50000000; -- system clock frequency in hz
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clock_frequency: integer := 50000000; -- system clock frequency in Hz
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debounce_counter_size: integer := 8); -- set such that (2^size)/clock_frequency = 5us (size = 8 for 50mhz)
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debounce_counter_size: integer := 8); -- set such that (2^size)/clock_frequency = 5us (size = 8 for 50MHz)
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port(
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port(
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clk: in std_ulogic; -- system clock
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clk: in std_ulogic; -- system clock
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ps2_clk: in std_ulogic; -- clock signal from PS/2 keyboard
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ps2_clk: in std_ulogic; -- clock signal from PS/2 keyboard
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ps2_data: in std_ulogic; -- data signal from PS/2 keyboard
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ps2_data: in std_ulogic; -- data signal from PS/2 keyboard
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ps2_code_new: out std_ulogic; -- flag that new PS/2 code is available on ps2_code bus
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ps2_code_new: out std_ulogic; -- flag that new PS/2 code is available on ps2_code bus
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ps2_code: out std_ulogic_vector(7 downto 0)); -- code received from PS/2
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ps2_code: out std_ulogic_vector(7 downto 0)); -- code received from PS/2
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end component;
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end component;
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component ps2_debounce is
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component ps2_debounce is
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generic(counter_size: integer := 19); --counter size (19 bits gives 10.5ms with 50mhz clock)
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generic(counter_size: integer := 19); --counter size (19 bits gives 10.5ms with 50MHz clock)
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port(
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port(
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clk: in std_ulogic;
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clk: in std_ulogic;
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button: in std_ulogic; --input signal to be debounced
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button: in std_ulogic; --input signal to be debounced
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result: out std_ulogic := '0'); --debounced signal
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result: out std_ulogic := '0'); --debounced signal
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end component;
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end component;
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component keyboard is
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component keyboard is
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generic(
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generic(
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clock_frequency: integer := 50000000; -- system clock frequency in hz
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g: common_generics;
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ps2_debounce_counter_size: integer := 8); -- set such that 2^size/clock_frequency = 5us (size = 8 for 50mhz)
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ps2_debounce_counter_size: integer := 8); -- set such that 2^size/clock_frequency = 5us (size = 8 for 50MHz)
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port(
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port(
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clk: in std_ulogic; -- system clock input
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clk: in std_ulogic; -- system clock input
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rst: in std_ulogic; -- system reset
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rst: in std_ulogic; -- system reset
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ps2_clk: in std_ulogic; -- clock signal from PS2 keyboard
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ps2_clk: in std_ulogic; -- clock signal from PS2 keyboard
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| Line 75... |
Line 76... |
kbd_char_buf: out std_ulogic_vector(6 downto 0)); -- ASCII value
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kbd_char_buf: out std_ulogic_vector(6 downto 0)); -- ASCII value
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end component;
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end component;
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end package;
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end package;
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------ Keyboard ----------------------------------------------------------------
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------ Keyboard ----------------------------------------------------------------
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library ieee;
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library ieee, work;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.kbd_pkg.all;
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use work.kbd_pkg.all;
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use work.util.common_generics;
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|
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entity keyboard is
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entity keyboard is
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generic(
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generic(
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clock_frequency: integer := 50000000; -- system clock frequency in hz
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g: common_generics;
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ps2_debounce_counter_size: integer := 8); -- set such that 2^size/clock_frequency = 5us (size = 8 for 50mhz)
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ps2_debounce_counter_size: integer := 8); -- set such that 2^size/clock_frequency = 5us (size = 8 for 50MHz)
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port(
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port(
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clk: in std_ulogic; -- system clock input
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clk: in std_ulogic; -- system clock input
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rst: in std_ulogic; -- system reset
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rst: in std_ulogic; -- system reset
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|
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ps2_clk: in std_ulogic; -- clock signal from PS2 keyboard
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ps2_clk: in std_ulogic; -- clock signal from PS2 keyboard
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| Line 100... |
Line 102... |
architecture rtl of keyboard is
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architecture rtl of keyboard is
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signal kbd_new_c, kbd_new_n: std_ulogic := '0';
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signal kbd_new_c, kbd_new_n: std_ulogic := '0';
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signal kbd_new_edge: std_ulogic := '0';
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signal kbd_new_edge: std_ulogic := '0';
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signal kbd_new: std_ulogic := '0'; -- new ASCII char available
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signal kbd_new: std_ulogic := '0'; -- new ASCII char available
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signal kbd_char: std_ulogic_vector(kbd_char_buf'range) := (others => '0'); -- ASCII char
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signal kbd_char: std_ulogic_vector(kbd_char_buf'range) := (others => '0'); -- ASCII char
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signal kbd_char_o: std_ulogic_vector(kbd_char_buf'range) := (others => '0'); -- ASCII char
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begin
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begin
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kbd_char_buf_new <= kbd_new_c;
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kbd_char_buf_new <= kbd_new_c after g.delay;
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ps2_next: process(clk, rst)
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ps2_next: process(clk, rst)
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begin
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begin
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if rst = '1' then
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if rst = '1' and g.asynchronous_reset then
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kbd_new_c <= '0';
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kbd_new_c <= '0' after g.delay;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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kbd_new_c <= kbd_new_n;
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if rst = '1' and not g.asynchronous_reset then
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kbd_new_c <= '0' after g.delay;
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else
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kbd_new_c <= kbd_new_n after g.delay;
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end if;
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end if;
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end if;
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end process;
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end process;
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new_char: entity work.reg
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new_char: entity work.reg
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generic map(N => kbd_char'high+1)
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generic map(g => g, N => kbd_char'length)
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port map(
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port map(
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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di => kbd_char,
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di => kbd_char,
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we => kbd_new_edge,
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we => kbd_new_edge,
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do => kbd_char_o);
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char_buf: entity work.reg
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generic map(N => kbd_char'high+1)
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port map(
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clk => clk,
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rst => rst,
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di => kbd_char_o,
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we => kbd_char_re,
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do => kbd_char_buf);
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do => kbd_char_buf);
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ps2_proc: process(kbd_new_edge, kbd_new_c, kbd_char_re)
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ps2_proc: process(kbd_new_edge, kbd_new_c, kbd_char_re)
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begin
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begin
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if kbd_new_edge = '1' then
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if kbd_new_edge = '1' then
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kbd_new_n <= '1';
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kbd_new_n <= '1' after g.delay;
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elsif kbd_char_re = '1' then
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elsif kbd_char_re = '1' then
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kbd_new_n <= '0';
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kbd_new_n <= '0' after g.delay;
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else
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else
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kbd_new_n <= kbd_new_c;
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kbd_new_n <= kbd_new_c after g.delay;
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end if;
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end if;
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end process;
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end process;
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-- Process a kbd_new into a single edge for the rest of the
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-- Process a kbd_new into a single edge for the rest of the
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-- system.
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-- system.
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ps2_edge_new_character_0: entity work.rising_edge_detector
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ps2_edge_new_character_0: entity work.rising_edge_detector
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generic map(g => g)
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port map(
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port map(
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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di => kbd_new,
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di => kbd_new,
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do => kbd_new_edge);
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do => kbd_new_edge);
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ps2_0: work.kbd_pkg.ps2_kbd_top
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ps2_0: work.kbd_pkg.ps2_kbd_top
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generic map(
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generic map(
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clock_frequency => clock_frequency,
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clock_frequency => g.clock_frequency,
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ps2_debounce_counter_size => ps2_debounce_counter_size)
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ps2_debounce_counter_size => ps2_debounce_counter_size)
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port map(
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port map(
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clk => clk,
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clk => clk,
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ps2_clk => ps2_clk,
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ps2_clk => ps2_clk,
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ps2_data => ps2_data,
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ps2_data => ps2_data,
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| Line 172... |
Line 169... |
use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.kbd_pkg.all;
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use work.kbd_pkg.all;
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|
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entity ps2_kbd_top is
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entity ps2_kbd_top is
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generic(
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generic(
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clock_frequency: integer := 50000000; -- system clock frequency in hz
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clock_frequency: integer := 50000000; -- system clock frequency in Hz
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ps2_debounce_counter_size: integer := 8); -- set such that 2^size/clock_frequency = 5us (size = 8 for 50mhz)
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ps2_debounce_counter_size: integer := 8); -- set such that 2^size/clock_frequency = 5us (size = 8 for 50MHz)
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port(
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port(
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clk: in std_ulogic; -- system clock input
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clk: in std_ulogic; -- system clock input
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ps2_clk: in std_ulogic; -- clock signal from PS2 keyboard
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ps2_clk: in std_ulogic; -- clock signal from PS2 keyboard
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ps2_data: in std_ulogic; -- data signal from PS2 keyboard
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ps2_data: in std_ulogic; -- data signal from PS2 keyboard
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ascii_new: out std_ulogic := '0'; -- output flag indicating new ascii value
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ascii_new: out std_ulogic := '0'; -- output flag indicating new ascii value
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| Line 485... |
Line 482... |
library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
|
|
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entity ps2_kbd_core is
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entity ps2_kbd_core is
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generic(
|
generic(
|
clock_frequency: integer := 50000000; -- system clock frequency in hz
|
clock_frequency: integer := 50000000; -- system clock frequency in Hz
|
debounce_counter_size: integer := 8); -- set such that (2^size)/clock_frequency = 5us (size = 8 for 50mhz)
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debounce_counter_size: integer := 8); -- set such that (2^size)/clock_frequency = 5us (size = 8 for 50MHz)
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port(
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port(
|
clk: in std_ulogic; -- system clock
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clk: in std_ulogic; -- system clock
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ps2_clk: in std_ulogic; -- clock signal from PS/2 keyboard
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ps2_clk: in std_ulogic; -- clock signal from PS/2 keyboard
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ps2_data: in std_ulogic; -- data signal from PS/2 keyboard
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ps2_data: in std_ulogic; -- data signal from PS/2 keyboard
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ps2_code_new: out std_ulogic; -- flag that new PS/2 code is available on ps2_code bus
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ps2_code_new: out std_ulogic; -- flag that new PS/2 code is available on ps2_code bus
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| Line 592... |
Line 589... |
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
|
|
entity ps2_debounce is
|
entity ps2_debounce is
|
generic(counter_size: integer := 19); --counter size (19 bits gives 10.5ms with 50mhz clock)
|
generic(counter_size: integer := 19); --counter size (19 bits gives 10.5ms with 50MHz clock)
|
port(
|
port(
|
clk: in std_ulogic;
|
clk: in std_ulogic;
|
button: in std_ulogic; --input signal to be debounced
|
button: in std_ulogic; --input signal to be debounced
|
result: out std_ulogic := '0'); --debounced signal
|
result: out std_ulogic := '0'); --debounced signal
|
end entity;
|
end entity;
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| Line 604... |
Line 601... |
architecture rtl of ps2_debounce is
|
architecture rtl of ps2_debounce is
|
signal flipflops: std_ulogic_vector(1 downto 0); --input flip flops
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signal flipflops: std_ulogic_vector(1 downto 0); --input flip flops
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signal counter_set: std_ulogic; --sync reset to zero
|
signal counter_set: std_ulogic; --sync reset to zero
|
signal counter_out: unsigned(counter_size downto 0) := (others => '0'); --counter output
|
signal counter_out: unsigned(counter_size downto 0) := (others => '0'); --counter output
|
begin
|
begin
|
|
|
counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter
|
counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter
|
|
|
process(clk)
|
process(clk)
|
begin
|
begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
flipflops(0) <= button;
|
flipflops(0) <= button;
|
flipflops(1) <= flipflops(0);
|
flipflops(1) <= flipflops(0);
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if(counter_set = '1') then --reset counter because input is changing
|
if counter_set = '1' then --reset counter because input is changing
|
counter_out <= (others => '0');
|
counter_out <= (others => '0');
|
elsif(counter_out(counter_size) = '0') then --stable input time is not yet met
|
elsif counter_out(counter_size) = '0' then --stable input time is not yet met
|
counter_out <= counter_out + 1;
|
counter_out <= counter_out + 1;
|
else --stable input time is met
|
else --stable input time is met
|
result <= flipflops(1);
|
result <= flipflops(1);
|
end if;
|
end if;
|
end if;
|
end if;
|
